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qmiga/qemu.git
2023-05-05
Richard Henderson
Merge tag 'migration-20230505-pull-request' of https...
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2023-05-05
Richard Henderson
Merge tag 'pull-riscv-to-apply-20230505-1' of https...
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2023-05-05
Rahul Pathak
target/riscv: add Ventana's Veyron V1 CPU
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2023-05-05
Alexandre Ghiti
riscv: Make sure an exception is raised if a pte is...
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2023-05-05
Irina Ryapolova
target/riscv: Fix Guest Physical Address Translation
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2023-05-05
Bin Meng
target/riscv: Restore the predicate() NULL check behavior
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2023-05-05
Daniel Henrique...
target/riscv: add TYPE_RISCV_DYNAMIC_CPU
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2023-05-05
Daniel Henrique...
target/riscv: add query-cpy-definitions support
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2023-05-05
Daniel Henrique...
target/riscv: add CPU QOM header
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2023-05-05
Ivan Klokov
hw/intc/riscv_aplic: Zero init APLIC internal state
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2023-05-05
Richard Henderson
target/riscv: Reorg sum check in get_physical_address
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2023-05-05
Richard Henderson
target/riscv: Reorg access check in get_physical_address
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2023-05-05
Richard Henderson
target/riscv: Merge checks for reserved pte flags
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2023-05-05
Richard Henderson
target/riscv: Don't modify SUM with is_debug
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2023-05-05
Richard Henderson
target/riscv: Suppress pte update with is_debug
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2023-05-05
Richard Henderson
target/riscv: Move leaf pte processing out of level...
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2023-05-05
Richard Henderson
target/riscv: Hoist pbmte and hade out of the level...
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2023-05-05
Richard Henderson
target/riscv: Hoist second stage mode change to callers
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2023-05-05
Richard Henderson
target/riscv: Check SUM in the correct register
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2023-05-05
Richard Henderson
target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index
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2023-05-05
Richard Henderson
target/riscv: Move hstatus.spvp check to check_access_hlsv
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2023-05-05
Richard Henderson
target/riscv: Introduce mmuidx_2stage
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2023-05-05
Richard Henderson
target/riscv: Introduce mmuidx_priv
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2023-05-05
Richard Henderson
target/riscv: Introduce mmuidx_sum
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2023-05-05
Richard Henderson
target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT
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2023-05-05
Richard Henderson
target/riscv: Handle HLV, HSV via helpers
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2023-05-05
Richard Henderson
target/riscv: Use cpu_ld*_code_mmu for HLVX
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2023-05-05
Fei Wu
target/riscv: Reduce overhead of MSTATUS_SUM change
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2023-05-05
Fei Wu
target/riscv: Separate priv from mmu_idx
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2023-05-05
LIU Zhiwei
target/riscv: Add a tb flags field for vstart
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2023-05-05
Richard Henderson
target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags
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2023-05-05
LIU Zhiwei
target/riscv: Encode the FS and VS on a normal way...
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2023-05-05
LIU Zhiwei
target/riscv: Add a general status enum for extensions
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2023-05-05
LIU Zhiwei
target/riscv: Extract virt enabled state from tb flags
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2023-05-05
Yi Chen
target/riscv: fix H extension TVM trap
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2023-05-05
Weiwei Li
target/riscv: Use check for relationship between Zdinx...
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2023-05-05
Weiwei Li
target/riscv: Legalize MPP value in write_mstatus
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2023-05-05
Weiwei Li
target/riscv: Use PRV_RESERVED instead of PRV_H
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2023-05-05
Weiwei Li
target/riscv: Fix the mstatus.MPP value after executing...
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2023-05-05
Daniel Henrique...
target/riscv/cpu.c: redesign register_cpu_props()
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2023-05-05
Daniel Henrique...
target/riscv: add RVG and remove cpu->cfg.ext_g
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2023-05-05
Daniel Henrique...
target/riscv: remove cfg.ext_g setup from rv64_thead_c9...
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2023-05-05
Daniel Henrique...
target/riscv: remove riscv_cpu_sync_misa_cfg()
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2023-05-05
Daniel Henrique...
target/riscv: remove cpu->cfg.ext_v
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2023-05-05
Daniel Henrique...
target/riscv: remove cpu->cfg.ext_j
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2023-05-05
Daniel Henrique...
target/riscv: remove cpu->cfg.ext_h
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2023-05-05
Daniel Henrique...
target/riscv: remove cpu->cfg.ext_u
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2023-05-05
Daniel Henrique...
target/riscv: remove cpu->cfg.ext_s
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2023-05-05
Daniel Henrique...
target/riscv: remove cpu->cfg.ext_m
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2023-05-05
Daniel Henrique...
target/riscv: remove cpu->cfg.ext_e
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2023-05-05
Daniel Henrique...
target/riscv: remove cpu->cfg.ext_i
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2023-05-05
Daniel Henrique...
target/riscv: remove cpu->cfg.ext_f
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2023-05-05
Daniel Henrique...
target/riscv: remove cpu->cfg.ext_d
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2023-05-05
Daniel Henrique...
target/riscv: remove cpu->cfg.ext_c
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2023-05-05
Daniel Henrique...
target/riscv: remove cpu->cfg.ext_a
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2023-05-05
Daniel Henrique...
target/riscv: introduce riscv_cpu_add_misa_properties()
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2023-05-05
Daniel Henrique...
target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data
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2023-05-05
Daniel Henrique...
target/riscv: remove MISA properties from isa_edata_arr[]
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2023-05-05
Daniel Henrique...
target/riscv: sync env->misa_ext* with cpu->cfg in...
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2023-05-05
Weiwei Li
hw/riscv: Add signature dump function for spike to...
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2023-05-05
Weiwei Li
target/riscv: Fix lines with over 80 characters
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2023-05-05
Weiwei Li
target/riscv: Fix format for comments
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2023-05-05
Weiwei Li
target/riscv: Fix format for indentation
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2023-05-05
Weiwei Li
target/riscv: Remove riscv_cpu_virt_enabled()
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2023-05-05
Weiwei Li
target/riscv: Set opcode to env->bins for illegal/virtu...
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2023-05-05
Weiwei Li
target/riscv: Fix addr type for get_physical_address
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2023-05-05
Weiwei Li
target/riscv: Remove redundant parentheses
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2023-05-05
LIU Zhiwei
target/riscv: Convert env->virt to a bool env->virt_enabled
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2023-05-05
Weiwei Li
target/riscv: Remove check on RVH for riscv_cpu_set_vir...
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2023-05-05
Weiwei Li
target/riscv: Remove check on RVH for riscv_cpu_virt_en...
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2023-05-05
Weiwei Li
target/riscv: Remove redundant check on RVH
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2023-05-05
Weiwei Li
target/riscv: Remove redundant call to riscv_cpu_virt_e...
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2023-05-05
LIU Zhiwei
target/riscv: Fix itrigger when icount is used
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2023-05-05
Weiwei Li
target/riscv: Add support for Zce
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2023-05-05
Weiwei Li
disas/riscv.c: add disasm support for Zc*
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2023-05-05
Weiwei Li
target/riscv: expose properties for Zc* extension
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2023-05-05
Weiwei Li
target/riscv: add support for Zcmt extension
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2023-05-05
Weiwei Li
target/riscv: add support for Zcmp extension
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2023-05-05
Weiwei Li
target/riscv: add support for Zcb extension
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2023-05-05
Weiwei Li
target/riscv: add support for Zcd extension
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2023-05-05
Weiwei Li
target/riscv: add support for Zcf extension
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2023-05-05
Weiwei Li
target/riscv: add support for Zca extension
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2023-05-05
Weiwei Li
target/riscv: add cfg properties for Zc* extension
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2023-05-05
Conor Dooley
target/riscv: fix invalid riscv,event-to-mhpmcounters...
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2023-05-05
Philipp Tomsich
target/riscv: redirect XVentanaCondOps to use the Zicon...
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2023-05-05
Philipp Tomsich
target/riscv: refactor Zicond support
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2023-05-05
Weiwei Li
target/riscv: Simplify arguments for riscv_csrrw_check
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2023-05-05
Weiwei Li
target/riscv: Simplify type conversion for CPURISCVState
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2023-05-05
Weiwei Li
target/riscv: Simplify getting RISCVCPU pointer from env
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2023-05-05
LIU Zhiwei
target/riscv: Fix priv version dependency for vector...
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2023-05-05
Weiwei Li
target/riscv: Avoid env_archcpu() when reading RISCVCPU...
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2023-05-05
Juan Quintela
qemu-file: Make ram_control_save_page() use accessors...
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2023-05-05
Juan Quintela
qemu-file: Make total_transferred an uint64_t
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2023-05-05
Juan Quintela
qemu-file: remove shutdown member
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2023-05-05
Juan Quintela
qemu-file: No need to check for shutdown in qemu_file_r...
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2023-05-04
Juan Quintela
migration: qemu_file_total_transferred() function is...
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2023-05-04
Juan Quintela
migration: max_postcopy_bandwidth is a size parameter
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2023-05-04
Juan Quintela
migration/rdma: Check for postcopy sooner
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2023-05-04
Juan Quintela
migration/rdma: It makes no sense to recive that flag...
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2023-05-04
Juan Quintela
migration/rdma: We can calculate the rioc from the...
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