* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
-*/
+ */
/**
* \file amdgpu.h
#include <stdint.h>
#include <stdbool.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
struct drm_amdgpu_info_hw_ip;
/*--------------------------------------------------------------------------*/
#define AMDGPU_CS_MAX_IBS_PER_SUBMIT 4
/**
- *
+ * Special timeout value meaning that the timeout is infinite.
*/
#define AMDGPU_TIMEOUT_INFINITE 0xffffffffffffffffull
/**
- * The special flag for GFX submission to identify that this is CE IB
- * \sa amdgpu_cs_ib_info
-*/
-#define AMDGPU_CS_GFX_IB_CE 0x1
-
-/**
- * The special flag to mark that this IB will re-used
- * by client and should not be automatically return back
- * to free pool by libdrm_amdgpu when submission is completed.
- *
- * \sa amdgpu_cs_ib_info
-*/
-#define AMDGPU_CS_REUSE_IB 0x2
-
-/**
- * The special resource flag for IB submission.
- * When VRAM is full, some resources may be moved to GTT to make place
- * for other resources which want to be in VRAM. This flag affects the order
- * in which resources are moved back to VRAM until there is no space there.
- * The resources with the highest priority will be moved first.
- * The value can be between 0 and 15, inclusive.
+ * Used in amdgpu_cs_query_fence_status(), meaning that the given timeout
+ * is absolute.
*/
-#define AMDGPU_IB_RESOURCE_PRIORITY(x) ((x) & 0xf)
-
+#define AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE (1 << 0)
/*--------------------------------------------------------------------------*/
/* ----------------------------- Enums ------------------------------------ */
amdgpu_bo_handle_type_dma_buf_fd = 2
};
-/**
- * Enum describing possible context reset states
- *
- * \sa amdgpu_cs_query_reset_state()
- *
-*/
-enum amdgpu_cs_ctx_reset_state {
- /** No reset was detected */
- amdgpu_cs_reset_no_error = 0,
-
- /** Reset/TDR was detected and context caused */
- amdgpu_cs_reset_guilty = 1,
-
- /** Reset/TDR was detected caused by other context */
- amdgpu_cs_reset_innocent = 2,
-
- /** Reset TDR was detected by cause of it unknown */
- amdgpu_cs_reset_unknown = 3
-};
-
-/**
- * For performance reasons and to simplify logic libdrm_amdgpu will handle
- * IBs only some pre-defined sizes.
- *
- * \sa amdgpu_cs_alloc_ib()
- */
-enum amdgpu_cs_ib_size {
- amdgpu_cs_ib_size_4K = 1,
- amdgpu_cs_ib_size_16K = 2,
- amdgpu_cs_ib_size_32K = 3,
- amdgpu_cs_ib_size_64K = 4,
- amdgpu_cs_ib_size_128K = 5
+/** Define known types of GPU VM VA ranges */
+enum amdgpu_gpu_va_range
+{
+ /** Allocate from "normal"/general range */
+ amdgpu_gpu_va_range_general = 0
};
-/** The number of different IB sizes */
-#define AMDGPU_CS_IB_SIZE_NUM 6
-
-
/*--------------------------------------------------------------------------*/
/* -------------------------- Datatypes ----------------------------------- */
/*--------------------------------------------------------------------------*/
typedef struct amdgpu_bo *amdgpu_bo_handle;
/**
- * Define handle to be used when dealing with command
- * buffers (a.k.a. ibs)
- *
+ * Define handle for list of BOs
*/
-typedef struct amdgpu_ib *amdgpu_ib_handle;
+typedef struct amdgpu_bo_list *amdgpu_bo_list_handle;
+/**
+ * Define handle to be used to work with VA allocated ranges
+ */
+typedef struct amdgpu_va *amdgpu_va_handle;
+
+/**
+ * Define handle for semaphore
+ */
+typedef struct amdgpu_semaphore *amdgpu_semaphore_handle;
/*--------------------------------------------------------------------------*/
/* -------------------------- Structures ---------------------------------- */
};
/**
- * Structure describing memory allocation request
- *
- * \sa amdgpu_bo_alloc()
-*/
-struct amdgpu_bo_alloc_result {
- /** Assigned virtual MC Base Address */
- uint64_t virtual_mc_base_address;
-
- /** Handle of allocated memory to be used by the given process only. */
- amdgpu_bo_handle buf_handle;
-};
-
-/**
* Special UMD specific information associated with buffer.
*
* It may be need to pass some buffer charactersitic as part
*/
uint64_t phys_alignment;
- /**
- * Assigned virtual MC Base Address.
- * \note This information will be returned only if this buffer was
- * allocated in the same process otherwise 0 will be returned.
- */
- uint64_t virtual_mc_base_address;
-
/** Heap where to allocate memory. */
uint32_t preferred_heap;
*/
struct amdgpu_bo_import_result {
/** Handle of memory/buffer to use */
- amdgpu_bo_handle buf_handle;
+ amdgpu_bo_handle buf_handle;
/** Buffer size */
uint64_t alloc_size;
-
- /** Assigned virtual MC Base Address */
- uint64_t virtual_mc_base_address;
};
-
/**
*
* Structure to describe GDS partitioning information.
*
*/
struct amdgpu_gds_resource_info {
- uint32_t gds_gfx_partition_size;
- uint32_t compute_partition_size;
- uint32_t gds_total_size;
- uint32_t gws_per_gfx_partition;
- uint32_t gws_per_compute_partition;
- uint32_t oa_per_gfx_partition;
- uint32_t oa_per_compute_partition;
+ uint32_t gds_gfx_partition_size;
+ uint32_t compute_partition_size;
+ uint32_t gds_total_size;
+ uint32_t gws_per_gfx_partition;
+ uint32_t gws_per_compute_partition;
+ uint32_t oa_per_gfx_partition;
+ uint32_t oa_per_compute_partition;
};
-
-
/**
- * Structure describing result of request to allocate GDS
+ * Structure describing CS fence
*
- * \sa amdgpu_gpu_resource_gds_alloc
+ * \sa amdgpu_cs_query_fence_status(), amdgpu_cs_request, amdgpu_cs_submit()
*
*/
-struct amdgpu_gds_alloc_info {
- /** Handle assigned to gds allocation */
- amdgpu_bo_handle resource_handle;
-
- /** How much was really allocated */
- uint32_t gds_memory_size;
+struct amdgpu_cs_fence {
- /** Number of GWS resources allocated */
- uint32_t gws;
+ /** In which context IB was sent to execution */
+ amdgpu_context_handle context;
- /** Number of OA resources allocated */
- uint32_t oa;
-};
+ /** To which HW IP type the fence belongs */
+ uint32_t ip_type;
-/**
- * Structure to described allocated command buffer (a.k.a. IB)
- *
- * \sa amdgpu_cs_alloc_ib()
- *
-*/
-struct amdgpu_cs_ib_alloc_result {
- /** IB allocation handle */
- amdgpu_ib_handle handle;
+ /** IP instance index if there are several IPs of the same type. */
+ uint32_t ip_instance;
- /** Assigned GPU VM MC Address of command buffer */
- uint64_t mc_address;
+ /** Ring index of the HW IP */
+ uint32_t ring;
- /** Address to be used for CPU access */
- void *cpu;
+ /** Specify fence for which we need to check submission status.*/
+ uint64_t fence;
};
/**
*/
struct amdgpu_cs_ib_info {
/** Special flags */
- uint64_t flags;
+ uint64_t flags;
- /** Handle of command buffer */
- amdgpu_ib_handle ib_handle;
+ /** Virtual MC address of the command buffer */
+ uint64_t ib_mc_address;
/**
* Size of Command Buffer to be submitted.
* - The size is in units of dwords (4 bytes).
- * - Must be less or equal to the size of allocated IB
* - Could be 0
*/
- uint32_t size;
+ uint32_t size;
+};
+
+/**
+ * Structure describing fence information
+ *
+ * \sa amdgpu_cs_request, amdgpu_cs_query_fence,
+ * amdgpu_cs_submit(), amdgpu_cs_query_fence_status()
+*/
+struct amdgpu_cs_fence_info {
+ /** buffer object for the fence */
+ amdgpu_bo_handle handle;
+
+ /** fence offset in the unit of sizeof(uint64_t) */
+ uint64_t offset;
};
/**
*/
struct amdgpu_cs_request {
/** Specify flags with additional information */
- uint64_t flags;
+ uint64_t flags;
/** Specify HW IP block type to which to send the IB. */
- unsigned ip_type;
+ unsigned ip_type;
/** IP instance index if there are several IPs of the same type. */
- unsigned ip_instance;
+ unsigned ip_instance;
/**
* Specify ring index of the IP. We could have several rings
* in the same IP. E.g. 0 for SDMA0 and 1 for SDMA1.
*/
- uint32_t ring;
+ uint32_t ring;
/**
- * Specify number of resource handles passed.
- * Size of 'handles' array
- *
+ * List handle with resources used by this request.
*/
- uint32_t number_of_resources;
+ amdgpu_bo_list_handle resources;
- /** Array of resources used by submission. */
- amdgpu_bo_handle *resources;
+ /**
+ * Number of dependencies this Command submission needs to
+ * wait for before starting execution.
+ */
+ uint32_t number_of_dependencies;
- /** Array of resources flags. This is optional and can be NULL. */
- uint8_t *resource_flags;
+ /**
+ * Array of dependencies which need to be met before
+ * execution can start.
+ */
+ struct amdgpu_cs_fence *dependencies;
/** Number of IBs to submit in the field ibs. */
uint32_t number_of_ibs;
* IBs to submit. Those IBs will be submit together as single entity
*/
struct amdgpu_cs_ib_info *ibs;
-};
-
-/**
- * Structure describing request to check submission state using fence
- *
- * \sa amdgpu_cs_query_fence_status()
- *
-*/
-struct amdgpu_cs_query_fence {
-
- /** In which context IB was sent to execution */
- amdgpu_context_handle context;
- /** Timeout in nanoseconds. */
- uint64_t timeout_ns;
-
- /** To which HW IP type the fence belongs */
- unsigned ip_type;
-
- /** IP instance index if there are several IPs of the same type. */
- unsigned ip_instance;
-
- /** Ring index of the HW IP */
- uint32_t ring;
-
- /** Flags */
- uint64_t flags;
+ /**
+ * The returned sequence number for the command submission
+ */
+ uint64_t seq_no;
- /** Specify fence for which we need to check
- * submission status.*/
- uint64_t fence;
+ /**
+ * The fence information
+ */
+ struct amdgpu_cs_fence_info fence_info;
};
/**
uint64_t size_remote;
};
-
/**
* Structure which provide information about heap
*
*/
struct amdgpu_heap_info {
/** Theoretical max. available memory in the given heap */
- uint64_t heap_size;
+ uint64_t heap_size;
/**
* Number of bytes allocated in the heap. This includes all processes
* are allocated, freed, and moved. It cannot be larger than
* heap_size.
*/
- uint64_t heap_usage;
+ uint64_t heap_usage;
/**
* Theoretical possible max. size of buffer which
* could be allocated in the given heap
*/
- uint64_t max_allocation;
+ uint64_t max_allocation;
};
-
-
/**
* Describe GPU h/w info needed for UMD correct initialization
*
struct amdgpu_gpu_info {
/** Asic id */
uint32_t asic_id;
- /**< Chip revision */
+ /** Chip revision */
uint32_t chip_rev;
/** Chip external revision */
uint32_t chip_external_rev;
uint64_t ids_flags;
/** max engine clock*/
uint64_t max_engine_clk;
+ /** max memory clock */
+ uint64_t max_memory_clk;
/** number of shader engines */
uint32_t num_shader_engines;
/** number of shader arrays per engine */
uint32_t num_hw_gfx_contexts;
/** Number of render backend pipes */
uint32_t rb_pipes;
- /** Active render backend pipe number */
- uint32_t active_rb_pipes;
/** Enabled render backend pipe mask */
uint32_t enabled_rb_pipes_mask;
/** Frequency of GPU Counter */
uint32_t cu_active_number;
uint32_t cu_ao_mask;
uint32_t cu_bitmap[4][4];
+ /* video memory type info*/
+ uint32_t vram_type;
+ /* video memory bit width*/
+ uint32_t vram_bit_width;
+ /** constant engine ram size*/
+ uint32_t ce_ram_size;
+ /* vce harvesting instance */
+ uint32_t vce_harvest_config;
+ /* PCI revision ID */
+ uint32_t pci_rev_id;
};
*
*/
-
/**
*
* \param fd - \c [in] File descriptor for AMD GPU device
* received previously as the result of
* e.g. drmOpen() call.
- * For legacy fd type, the DRI2/DRI3 authentication
- * should be done before calling this function.
+ * For legacy fd type, the DRI2/DRI3
+ * authentication should be done before
+ * calling this function.
* \param major_version - \c [out] Major version of library. It is assumed
* that adding new functionality will cause
* increase in major version
*
*
* \return 0 on success\n
- * >0 - AMD specific error code\n
* <0 - Negative POSIX Error code
*
*
uint32_t *minor_version,
amdgpu_device_handle *device_handle);
-
-
/**
*
* When access to such library does not needed any more the special
* result e.g. of drmOpen() call.
*
* \return 0 on success\n
- * >0 - AMD specific error code\n
* <0 - Negative POSIX Error code
*
* \sa amdgpu_device_initialize()
*/
int amdgpu_device_deinitialize(amdgpu_device_handle device_handle);
-
/*
* Memory Management
*
* See #amdgpu_device_initialize()
* \param alloc_buffer - \c [in] Pointer to the structure describing an
* allocation request
- * \param info - \c [out] Pointer to structure which return
- * information about allocated memory
+ * \param buf_handle - \c [out] Allocated buffer handle
*
* \return 0 on success\n
- * >0 - AMD specific error code\n
* <0 - Negative POSIX Error code
*
* \sa amdgpu_bo_free()
*/
int amdgpu_bo_alloc(amdgpu_device_handle dev,
struct amdgpu_bo_alloc_request *alloc_buffer,
- struct amdgpu_bo_alloc_result *info);
+ amdgpu_bo_handle *buf_handle);
/**
* Associate opaque data with buffer to be queried by another UMD
* \param info - \c [in] Metadata to associated with buffer
*
* \return 0 on success\n
- * >0 - AMD specific error code\n
* <0 - Negative POSIX Error code
*/
int amdgpu_bo_set_metadata(amdgpu_bo_handle buf_handle,
* \param info - \c [out] Structure describing buffer
*
* \return 0 on success\n
- * >0 - AMD specific error code\n
* <0 - Negative POSIX Error code
*
* \sa amdgpu_bo_set_metadata(), amdgpu_bo_alloc()
* \param shared_handle - \c [out] Special "shared" handle
*
* \return 0 on success\n
- * >0 - AMD specific error code\n
* <0 - Negative POSIX Error code
*
* \sa amdgpu_bo_import()
* about imported buffer
*
* \return 0 on success\n
- * >0 - AMD specific error code\n
* <0 - Negative POSIX Error code
*
* \note Buffer must be "imported" only using new "fd" (different from
struct amdgpu_bo_import_result *output);
/**
+ * Request GPU access to user allocated memory e.g. via "malloc"
+ *
+ * \param dev - [in] Device handle. See #amdgpu_device_initialize()
+ * \param cpu - [in] CPU address of user allocated memory which we
+ * want to map to GPU address space (make GPU accessible)
+ * (This address must be correctly aligned).
+ * \param size - [in] Size of allocation (must be correctly aligned)
+ * \param buf_handle - [out] Buffer handle for the userptr memory
+ * resource on submission and be used in other operations.
+ *
+ *
+ * \return 0 on success\n
+ * <0 - Negative POSIX Error code
+ *
+ * \note
+ * This call doesn't guarantee that such memory will be persistently
+ * "locked" / make non-pageable. The purpose of this call is to provide
+ * opportunity for GPU get access to this resource during submission.
+ *
+ * The maximum amount of memory which could be mapped in this call depends
+ * if overcommit is disabled or not. If overcommit is disabled than the max.
+ * amount of memory to be pinned will be limited by left "free" size in total
+ * amount of memory which could be locked simultaneously ("GART" size).
+ *
+ * Supported (theoretical) max. size of mapping is restricted only by
+ * "GART" size.
+ *
+ * It is responsibility of caller to correctly specify access rights
+ * on VA assignment.
+*/
+int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev,
+ void *cpu, uint64_t size,
+ amdgpu_bo_handle *buf_handle);
+
+/**
* Free previosuly allocated memory
*
* \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
* \param buf_handle - \c [in] Buffer handle to free
*
* \return 0 on success\n
- * >0 - AMD specific error code\n
* <0 - Negative POSIX Error code
*
* \note In the case of memory shared between different applications all
int amdgpu_bo_free(amdgpu_bo_handle buf_handle);
/**
- * Request CPU access to GPU accessable memory
+ * Request CPU access to GPU accessible memory
*
* \param buf_handle - \c [in] Buffer handle
* \param cpu - \c [out] CPU address to be used for access
*
* \return 0 on success\n
- * >0 - AMD specific error code\n
* <0 - Negative POSIX Error code
*
* \sa amdgpu_bo_cpu_unmap()
* \param buf_handle - \c [in] Buffer handle
*
* \return 0 on success\n
- * >0 - AMD specific error code\n
* <0 - Negative POSIX Error code
*
* \sa amdgpu_bo_cpu_map()
*/
int amdgpu_bo_cpu_unmap(amdgpu_bo_handle buf_handle);
-
/**
* Wait until a buffer is not used by the device.
*
- * \param dev - \c [in] Device handle. See #amdgpu_lib_initialize()
+ * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
* \param buf_handle - \c [in] Buffer handle.
* \param timeout_ns - Timeout in nanoseconds.
* \param buffer_busy - 0 if buffer is idle, all GPU access was completed
* 1 GPU access is in fly or scheduled
*
* \return 0 - on success
- * <0 - AMD specific error code
+ * <0 - Negative POSIX Error code
*/
int amdgpu_bo_wait_for_idle(amdgpu_bo_handle buf_handle,
uint64_t timeout_ns,
bool *buffer_busy);
-
-/*
- * Special GPU Resources
- *
-*/
-
-
-
/**
- * Query information about GDS
+ * Creates a BO list handle for command submission.
*
- * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
- * \param gds_info - \c [out] Pointer to structure to get GDS information
+ * \param dev - \c [in] Device handle.
+ * See #amdgpu_device_initialize()
+ * \param number_of_resources - \c [in] Number of BOs in the list
+ * \param resources - \c [in] List of BO handles
+ * \param resource_prios - \c [in] Optional priority for each handle
+ * \param result - \c [out] Created BO list handle
*
* \return 0 on success\n
- * >0 - AMD specific error code\n
* <0 - Negative POSIX Error code
*
+ * \sa amdgpu_bo_list_destroy()
*/
-int amdgpu_gpu_resource_query_gds_info(amdgpu_device_handle dev,
- struct amdgpu_gds_resource_info *
- gds_info);
-
+int amdgpu_bo_list_create(amdgpu_device_handle dev,
+ uint32_t number_of_resources,
+ amdgpu_bo_handle *resources,
+ uint8_t *resource_prios,
+ amdgpu_bo_list_handle *result);
/**
- * Allocate GDS partitions
+ * Destroys a BO list handle.
*
- * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
- * \param gds_size - \c [in] Size of gds allocation. Must be aligned
- * accordingly.
- * \param alloc_info - \c [out] Pointer to structure to receive information
- * about allocation
+ * \param handle - \c [in] BO list handle.
*
* \return 0 on success\n
- * >0 - AMD specific error code\n
* <0 - Negative POSIX Error code
*
- *
+ * \sa amdgpu_bo_list_create()
*/
-int amdgpu_gpu_resource_gds_alloc(amdgpu_device_handle dev,
- uint32_t gds_size,
- struct amdgpu_gds_alloc_info *alloc_info);
-
-
-
+int amdgpu_bo_list_destroy(amdgpu_bo_list_handle handle);
/**
- * Release GDS resource. When GDS and associated resources not needed any
- * more UMD should free them
+ * Update resources for existing BO list
*
- * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
- * \param handle - \c [in] Handle assigned to GDS allocation
+ * \param handle - \c [in] BO list handle
+ * \param number_of_resources - \c [in] Number of BOs in the list
+ * \param resources - \c [in] List of BO handles
+ * \param resource_prios - \c [in] Optional priority for each handle
*
* \return 0 on success\n
- * >0 - AMD specific error code\n
* <0 - Negative POSIX Error code
*
+ * \sa amdgpu_bo_list_update()
*/
-int amdgpu_gpu_resource_gds_free(amdgpu_bo_handle handle);
-
-
+int amdgpu_bo_list_update(amdgpu_bo_list_handle handle,
+ uint32_t number_of_resources,
+ amdgpu_bo_handle *resources,
+ uint8_t *resource_prios);
/*
* GPU Execution context
* \param context - \c [out] GPU Context handle
*
* \return 0 on success\n
- * >0 - AMD specific error code\n
* <0 - Negative POSIX Error code
*
* \sa amdgpu_cs_ctx_free()
* \param context - \c [in] GPU Context handle
*
* \return 0 on success\n
- * >0 - AMD specific error code\n
* <0 - Negative POSIX Error code
*
* \sa amdgpu_cs_ctx_create()
* Query reset state for the specific GPU Context
*
* \param context - \c [in] GPU Context handle
- * \param state - \c [out] Reset state status
+ * \param state - \c [out] One of AMDGPU_CTX_*_RESET
+ * \param hangs - \c [out] Number of hangs caused by the context.
*
* \return 0 on success\n
- * >0 - AMD specific error code\n
* <0 - Negative POSIX Error code
*
* \sa amdgpu_cs_ctx_create()
*
*/
int amdgpu_cs_query_reset_state(amdgpu_context_handle context,
- enum amdgpu_cs_ctx_reset_state *state);
-
+ uint32_t *state, uint32_t *hangs);
/*
* Command Buffers Management
*
*/
-
-/**
- * Allocate memory to be filled with PM4 packets and be served as the first
- * entry point of execution (a.k.a. Indirect Buffer)
- *
- * \param context - \c [in] GPU Context which will use IB
- * \param ib_size - \c [in] Size of allocation
- * \param output - \c [out] Pointer to structure to get information about
- * allocated IB
- *
- * \return 0 on success\n
- * >0 - AMD specific error code\n
- * <0 - Negative POSIX Error code
- *
- * \sa amdgpu_cs_free_ib()
- *
-*/
-int amdgpu_cs_alloc_ib(amdgpu_context_handle context,
- enum amdgpu_cs_ib_size ib_size,
- struct amdgpu_cs_ib_alloc_result *output);
-
-/**
- * If UMD has allocates IBs which doesn’t need any more than those IBs must
- * be explicitly freed
- *
- * \param handle - \c [in] IB handle
- *
- * \return 0 on success\n
- * >0 - AMD specific error code\n
- * <0 - Negative POSIX Error code
- *
- * \note Libdrm_amdgpu will guarantee that it will correctly detect when it
- * is safe to return IB to free pool
- *
- * \sa amdgpu_cs_alloc_ib()
- *
-*/
-int amdgpu_cs_free_ib(amdgpu_ib_handle handle);
-
/**
* Send request to submit command buffers to hardware.
*
* from the same GPU context to the same ip:ip_instance:ring will be executed in
* order.
*
+ * The caller can specify the user fence buffer/location with the fence_info in the
+ * cs_request.The sequence number is returned via the 'seq_no' parameter
+ * in ibs_request structure.
+ *
*
* \param dev - \c [in] Device handle.
* See #amdgpu_device_initialize()
* \param context - \c [in] GPU Context
* \param flags - \c [in] Global submission flags
- * \param ibs_request - \c [in] Pointer to submission requests.
+ * \param ibs_request - \c [in/out] Pointer to submission requests.
* We could submit to the several
* engines/rings simulteniously as
* 'atomic' operation
* \param number_of_requests - \c [in] Number of submission requests
- * \param fences - \c [out] Pointer to array of data to get
- * fences to identify submission
- * requests. Timestamps are valid
- * in this GPU context and could be used
- * to identify/detect completion of
- * submission request
*
* \return 0 on success\n
- * >0 - AMD specific error code\n
* <0 - Negative POSIX Error code
*
- * \note It is assumed that by default IB will be returned to free pool
- * automatically by libdrm_amdgpu when submission will completed.
- * It is possible for UMD to make decision to re-use the same IB in
- * this case it should be explicitly freed.\n
- * Accordingly, by default, after submission UMD should not touch passed
- * IBs. If UMD needs to re-use IB then the special flag AMDGPU_CS_REUSE_IB
- * must be passed.
- *
* \note It is required to pass correct resource list with buffer handles
* which will be accessible by command buffers from submission
* This will allow kernel driver to correctly implement "paging".
int amdgpu_cs_submit(amdgpu_context_handle context,
uint64_t flags,
struct amdgpu_cs_request *ibs_request,
- uint32_t number_of_requests,
- uint64_t *fences);
+ uint32_t number_of_requests);
/**
* Query status of Command Buffer Submission
*
- * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
* \param fence - \c [in] Structure describing fence to query
+ * \param timeout_ns - \c [in] Timeout value to wait
+ * \param flags - \c [in] Flags for the query
* \param expired - \c [out] If fence expired or not.\n
* 0 – if fence is not expired\n
* !0 - otherwise
*
* \return 0 on success\n
- * >0 - AMD specific error code\n
* <0 - Negative POSIX Error code
*
* \note If UMD wants only to check operation status and returned immediately
*
* \sa amdgpu_cs_submit()
*/
-int amdgpu_cs_query_fence_status(struct amdgpu_cs_query_fence *fence,
+int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence,
+ uint64_t timeout_ns,
+ uint64_t flags,
uint32_t *expired);
+/**
+ * Wait for multiple fences
+ *
+ * \param fences - \c [in] The fence array to wait
+ * \param fence_count - \c [in] The fence count
+ * \param wait_all - \c [in] If true, wait all fences to be signaled,
+ * otherwise, wait at least one fence
+ * \param timeout_ns - \c [in] The timeout to wait, in nanoseconds
+ * \param status - \c [out] '1' for signaled, '0' for timeout
+ * \param first - \c [out] the index of the first signaled fence from @fences
+ *
+ * \return 0 on success
+ * <0 - Negative POSIX Error code
+ *
+ * \note Currently it supports only one amdgpu_device. All fences come from
+ * the same amdgpu_device with the same fd.
+*/
+int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences,
+ uint32_t fence_count,
+ bool wait_all,
+ uint64_t timeout_ns,
+ uint32_t *status, uint32_t *first);
/*
* Query / Info API
*
*/
-
/**
* Query allocation size alignments
*
* requirements
*
* \return 0 on success\n
- * >0 - AMD specific error code\n
* <0 - Negative POSIX Error code
*
*/
int amdgpu_query_buffer_size_alignment(amdgpu_device_handle dev,
- struct amdgpu_buffer_size_alignments
- *info);
-
-
+ struct amdgpu_buffer_size_alignments
+ *info);
/**
* Query firmware versions
* \param feature - \c [out] Pointer to to the "feature" return value
*
* \return 0 on success\n
- * >0 - AMD specific error code\n
* <0 - Negative POSIX Error code
*
*/
unsigned ip_instance, unsigned index,
uint32_t *version, uint32_t *feature);
-
-
/**
* Query the number of HW IP instances of a certain type.
*
* \param count - \c [out] Pointer to structure to get information
*
* \return 0 on success\n
- * >0 - AMD specific error code\n
* <0 - Negative POSIX Error code
*/
int amdgpu_query_hw_ip_count(amdgpu_device_handle dev, unsigned type,
uint32_t *count);
-
-
/**
* Query engine information
*
* \param info - \c [out] Pointer to structure to get information
*
* \return 0 on success\n
- * >0 - AMD specific error code\n
* <0 - Negative POSIX Error code
*/
int amdgpu_query_hw_ip_info(amdgpu_device_handle dev, unsigned type,
unsigned ip_instance,
struct drm_amdgpu_info_hw_ip *info);
-
-
-
/**
* Query heap information
*
* \param info - \c [in] Pointer to structure to get needed information
*
* \return 0 on success\n
- * >0 - AMD specific error code\n
* <0 - Negative POSIX Error code
*
*/
-int amdgpu_query_heap_info(amdgpu_device_handle dev,
- uint32_t heap,
- uint32_t flags,
- struct amdgpu_heap_info *info);
-
-
+int amdgpu_query_heap_info(amdgpu_device_handle dev, uint32_t heap,
+ uint32_t flags, struct amdgpu_heap_info *info);
/**
* Get the CRTC ID from the mode object ID
* \param result - \c [in] Pointer to the CRTC ID
*
* \return 0 on success\n
- * >0 - AMD specific error code\n
* <0 - Negative POSIX Error code
*
*/
int amdgpu_query_crtc_from_id(amdgpu_device_handle dev, unsigned id,
int32_t *result);
-
-
/**
* Query GPU H/w Info
*
* \param info - \c [in] Pointer to structure to get needed information
*
* \return 0 on success\n
- * >0 - AMD specific error code\n
* <0 - Negative POSIX Error code
*
*/
int amdgpu_query_gpu_info(amdgpu_device_handle dev,
struct amdgpu_gpu_info *info);
-
-
/**
* Query hardware or driver information.
*
* \param value - \c [out] Pointer to the return value.
*
* \return 0 on success\n
- * >0 - AMD specific error code\n
* <0 - Negative POSIX error code
*
*/
int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id,
unsigned size, void *value);
+/**
+ * Query information about GDS
+ *
+ * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
+ * \param gds_info - \c [out] Pointer to structure to get GDS information
+ *
+ * \return 0 on success\n
+ * <0 - Negative POSIX Error code
+ *
+*/
+int amdgpu_query_gds_info(amdgpu_device_handle dev,
+ struct amdgpu_gds_resource_info *gds_info);
+/**
+ * Query information about sensor.
+ *
+ * The return size is query-specific and depends on the "sensor_type"
+ * parameter. No more than "size" bytes is returned.
+ *
+ * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
+ * \param sensor_type - \c [in] AMDGPU_INFO_SENSOR_*
+ * \param size - \c [in] Size of the returned value.
+ * \param value - \c [out] Pointer to the return value.
+ *
+ * \return 0 on success\n
+ * <0 - Negative POSIX Error code
+ *
+*/
+int amdgpu_query_sensor_info(amdgpu_device_handle dev, unsigned sensor_type,
+ unsigned size, void *value);
/**
* Read a set of consecutive memory-mapped registers.
* \param values - \c [out] The pointer to return values.
*
* \return 0 on success\n
- * >0 - AMD specific error code\n
* <0 - Negative POSIX error code
*
*/
unsigned count, uint32_t instance, uint32_t flags,
uint32_t *values);
-
+/**
+ * Flag to request VA address range in the 32bit address space
+*/
+#define AMDGPU_VA_RANGE_32_BIT 0x1
/**
- * Request GPU access to user allocated memory e.g. via "malloc"
+ * Allocate virtual address range
*
* \param dev - [in] Device handle. See #amdgpu_device_initialize()
- * \param cpu - [in] CPU address of user allocated memory which we
- * want to map to GPU address space (make GPU accessible)
- * (This address must be correctly aligned).
- * \param size - [in] Size of allocation (must be correctly aligned)
- * \param amdgpu_bo_alloc_result - [out] Handle of allocation to be passed as resource
- * on submission and be used in other operations.(e.g. for VA submission)
- * ( Temporally defined amdgpu_bo_alloc_result as parameter for return mc address. )
+ * \param va_range_type - \c [in] Type of MC va range from which to allocate
+ * \param size - \c [in] Size of range. Size must be correctly* aligned.
+ * It is client responsibility to correctly aligned size based on the future
+ * usage of allocated range.
+ * \param va_base_alignment - \c [in] Overwrite base address alignment
+ * requirement for GPU VM MC virtual
+ * address assignment. Must be multiple of size alignments received as
+ * 'amdgpu_buffer_size_alignments'.
+ * If 0 use the default one.
+ * \param va_base_required - \c [in] Specified required va base address.
+ * If 0 then library choose available one.
+ * If !0 value will be passed and those value already "in use" then
+ * corresponding error status will be returned.
+ * \param va_base_allocated - \c [out] On return: Allocated VA base to be used
+ * by client.
+ * \param va_range_handle - \c [out] On return: Handle assigned to allocation
+ * \param flags - \c [in] flags for special VA range
+ *
+ * \return 0 on success\n
+ * >0 - AMD specific error code\n
+ * <0 - Negative POSIX Error code
*
+ * \notes \n
+ * It is client responsibility to correctly handle VA assignments and usage.
+ * Neither kernel driver nor libdrm_amdpgu are able to prevent and
+ * detect wrong va assignemnt.
*
- * \return 0 on success
- * >0 - AMD specific error code
+ * It is client responsibility to correctly handle multi-GPU cases and to pass
+ * the corresponding arrays of all devices handles where corresponding VA will
+ * be used.
+ *
+*/
+int amdgpu_va_range_alloc(amdgpu_device_handle dev,
+ enum amdgpu_gpu_va_range va_range_type,
+ uint64_t size,
+ uint64_t va_base_alignment,
+ uint64_t va_base_required,
+ uint64_t *va_base_allocated,
+ amdgpu_va_handle *va_range_handle,
+ uint64_t flags);
+
+/**
+ * Free previously allocated virtual address range
+ *
+ *
+ * \param va_range_handle - \c [in] Handle assigned to VA allocation
+ *
+ * \return 0 on success\n
+ * >0 - AMD specific error code\n
* <0 - Negative POSIX Error code
*
+*/
+int amdgpu_va_range_free(amdgpu_va_handle va_range_handle);
+
+/**
+* Query virtual address range
+*
+* UMD can query GPU VM range supported by each device
+* to initialize its own VAM accordingly.
+*
+* \param dev - [in] Device handle. See #amdgpu_device_initialize()
+* \param type - \c [in] Type of virtual address range
+* \param offset - \c [out] Start offset of virtual address range
+* \param size - \c [out] Size of virtual address range
+*
+* \return 0 on success\n
+* <0 - Negative POSIX Error code
+*
+*/
+
+int amdgpu_va_range_query(amdgpu_device_handle dev,
+ enum amdgpu_gpu_va_range type,
+ uint64_t *start,
+ uint64_t *end);
+
+/**
+ * VA mapping/unmapping for the buffer object
*
- * \note
- * This call doesn't guarantee that such memory will be persistently
- * "locked" / make non-pageable. The purpose of this call is to provide
- * opportunity for GPU get access to this resource during submission.
+ * \param bo - \c [in] BO handle
+ * \param offset - \c [in] Start offset to map
+ * \param size - \c [in] Size to map
+ * \param addr - \c [in] Start virtual address.
+ * \param flags - \c [in] Supported flags for mapping/unmapping
+ * \param ops - \c [in] AMDGPU_VA_OP_MAP or AMDGPU_VA_OP_UNMAP
*
- * The maximum amount of memory which could be mapped in this call depends
- * if overcommit is disabled or not. If overcommit is disabled than the max.
- * amount of memory to be pinned will be limited by left "free" size in total
- * amount of memory which could be locked simultaneously ("GART" size).
+ * \return 0 on success\n
+ * <0 - Negative POSIX Error code
*
- * Supported (theoretical) max. size of mapping is restricted only by
- * "GART" size.
+*/
+
+int amdgpu_bo_va_op(amdgpu_bo_handle bo,
+ uint64_t offset,
+ uint64_t size,
+ uint64_t addr,
+ uint64_t flags,
+ uint32_t ops);
+
+/**
+ * VA mapping/unmapping for a buffer object or PRT region.
+ *
+ * This is not a simple drop-in extension for amdgpu_bo_va_op; instead, all
+ * parameters are treated "raw", i.e. size is not automatically aligned, and
+ * all flags must be specified explicitly.
+ *
+ * \param dev - \c [in] device handle
+ * \param bo - \c [in] BO handle (may be NULL)
+ * \param offset - \c [in] Start offset to map
+ * \param size - \c [in] Size to map
+ * \param addr - \c [in] Start virtual address.
+ * \param flags - \c [in] Supported flags for mapping/unmapping
+ * \param ops - \c [in] AMDGPU_VA_OP_MAP or AMDGPU_VA_OP_UNMAP
+ *
+ * \return 0 on success\n
+ * <0 - Negative POSIX Error code
*
- * It is responsibility of caller to correctly specify access rights
- * on VA assignment.
*/
-int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev,
- void *cpu,
- uint64_t size,
- struct amdgpu_bo_alloc_result *info);
+int amdgpu_bo_va_op_raw(amdgpu_device_handle dev,
+ amdgpu_bo_handle bo,
+ uint64_t offset,
+ uint64_t size,
+ uint64_t addr,
+ uint64_t flags,
+ uint32_t ops);
+
+/**
+ * create semaphore
+ *
+ * \param sem - \c [out] semaphore handle
+ *
+ * \return 0 on success\n
+ * <0 - Negative POSIX Error code
+ *
+*/
+int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem);
+
+/**
+ * signal semaphore
+ *
+ * \param context - \c [in] GPU Context
+ * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_*
+ * \param ip_instance - \c [in] Index of the IP block of the same type
+ * \param ring - \c [in] Specify ring index of the IP
+ * \param sem - \c [in] semaphore handle
+ *
+ * \return 0 on success\n
+ * <0 - Negative POSIX Error code
+ *
+*/
+int amdgpu_cs_signal_semaphore(amdgpu_context_handle ctx,
+ uint32_t ip_type,
+ uint32_t ip_instance,
+ uint32_t ring,
+ amdgpu_semaphore_handle sem);
+
+/**
+ * wait semaphore
+ *
+ * \param context - \c [in] GPU Context
+ * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_*
+ * \param ip_instance - \c [in] Index of the IP block of the same type
+ * \param ring - \c [in] Specify ring index of the IP
+ * \param sem - \c [in] semaphore handle
+ *
+ * \return 0 on success\n
+ * <0 - Negative POSIX Error code
+ *
+*/
+int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx,
+ uint32_t ip_type,
+ uint32_t ip_instance,
+ uint32_t ring,
+ amdgpu_semaphore_handle sem);
+
+/**
+ * destroy semaphore
+ *
+ * \param sem - \c [in] semaphore handle
+ *
+ * \return 0 on success\n
+ * <0 - Negative POSIX Error code
+ *
+*/
+int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem);
+
+/**
+ * Get the ASIC marketing name
+ *
+ * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
+ *
+ * \return the constant string of the marketing name
+ * "NULL" means the ASIC is not found
+*/
+const char *amdgpu_get_marketing_name(amdgpu_device_handle dev);
+
+#ifdef __cplusplus
+}
+#endif
#endif /* #ifdef _AMDGPU_H_ */
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