return 0;
}
-int amdgpu_bo_alloc(amdgpu_device_handle dev,
- struct amdgpu_bo_alloc_request *alloc_buffer,
- amdgpu_bo_handle *buf_handle)
+drm_public int amdgpu_bo_alloc(amdgpu_device_handle dev,
+ struct amdgpu_bo_alloc_request *alloc_buffer,
+ amdgpu_bo_handle *buf_handle)
{
union drm_amdgpu_gem_create args;
int r;
return r;
}
-int amdgpu_bo_set_metadata(amdgpu_bo_handle bo,
- struct amdgpu_bo_metadata *info)
+drm_public int amdgpu_bo_set_metadata(amdgpu_bo_handle bo,
+ struct amdgpu_bo_metadata *info)
{
struct drm_amdgpu_gem_metadata args = {};
&args, sizeof(args));
}
-int amdgpu_bo_query_info(amdgpu_bo_handle bo,
- struct amdgpu_bo_info *info)
+drm_public int amdgpu_bo_query_info(amdgpu_bo_handle bo,
+ struct amdgpu_bo_info *info)
{
struct drm_amdgpu_gem_metadata metadata = {};
struct drm_amdgpu_gem_create_in bo_info = {};
return r;
}
-int amdgpu_bo_export(amdgpu_bo_handle bo,
- enum amdgpu_bo_handle_type type,
- uint32_t *shared_handle)
+drm_public int amdgpu_bo_export(amdgpu_bo_handle bo,
+ enum amdgpu_bo_handle_type type,
+ uint32_t *shared_handle)
{
int r;
return -EINVAL;
}
-int amdgpu_bo_import(amdgpu_device_handle dev,
- enum amdgpu_bo_handle_type type,
- uint32_t shared_handle,
+drm_public int amdgpu_bo_import(amdgpu_device_handle dev,
+ enum amdgpu_bo_handle_type type,
+ uint32_t shared_handle,
struct amdgpu_bo_import_result *output)
{
struct drm_gem_open open_arg = {};
return r;
}
-int amdgpu_bo_free(amdgpu_bo_handle buf_handle)
+drm_public int amdgpu_bo_free(amdgpu_bo_handle buf_handle)
{
struct amdgpu_device *dev;
struct amdgpu_bo *bo = buf_handle;
return 0;
}
-void amdgpu_bo_inc_ref(amdgpu_bo_handle bo)
+drm_public void amdgpu_bo_inc_ref(amdgpu_bo_handle bo)
{
atomic_inc(&bo->refcount);
}
-int amdgpu_bo_cpu_map(amdgpu_bo_handle bo, void **cpu)
+drm_public int amdgpu_bo_cpu_map(amdgpu_bo_handle bo, void **cpu)
{
union drm_amdgpu_gem_mmap args;
void *ptr;
return 0;
}
-int amdgpu_bo_cpu_unmap(amdgpu_bo_handle bo)
+drm_public int amdgpu_bo_cpu_unmap(amdgpu_bo_handle bo)
{
int r;
return r;
}
-int amdgpu_query_buffer_size_alignment(amdgpu_device_handle dev,
+drm_public int amdgpu_query_buffer_size_alignment(amdgpu_device_handle dev,
struct amdgpu_buffer_size_alignments *info)
{
info->size_local = dev->dev_info.pte_fragment_size;
return 0;
}
-int amdgpu_bo_wait_for_idle(amdgpu_bo_handle bo,
- uint64_t timeout_ns,
+drm_public int amdgpu_bo_wait_for_idle(amdgpu_bo_handle bo,
+ uint64_t timeout_ns,
bool *busy)
{
union drm_amdgpu_gem_wait_idle args;
}
}
-int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev,
- void *cpu,
- uint64_t size,
- amdgpu_bo_handle *buf_handle,
- uint64_t *offset_in_bo)
+drm_public int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev,
+ void *cpu,
+ uint64_t size,
+ amdgpu_bo_handle *buf_handle,
+ uint64_t *offset_in_bo)
{
struct amdgpu_bo *bo;
uint32_t i;
return r;
}
-int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev,
- void *cpu,
- uint64_t size,
- amdgpu_bo_handle *buf_handle)
+drm_public int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev,
+ void *cpu,
+ uint64_t size,
+ amdgpu_bo_handle *buf_handle)
{
int r;
struct drm_amdgpu_gem_userptr args;
return r;
}
-int amdgpu_bo_list_create(amdgpu_device_handle dev,
- uint32_t number_of_resources,
- amdgpu_bo_handle *resources,
- uint8_t *resource_prios,
- amdgpu_bo_list_handle *result)
+drm_public int amdgpu_bo_list_create(amdgpu_device_handle dev,
+ uint32_t number_of_resources,
+ amdgpu_bo_handle *resources,
+ uint8_t *resource_prios,
+ amdgpu_bo_list_handle *result)
{
struct drm_amdgpu_bo_list_entry *list;
union drm_amdgpu_bo_list args;
return 0;
}
-int amdgpu_bo_list_destroy(amdgpu_bo_list_handle list)
+drm_public int amdgpu_bo_list_destroy(amdgpu_bo_list_handle list)
{
union drm_amdgpu_bo_list args;
int r;
return r;
}
-int amdgpu_bo_list_update(amdgpu_bo_list_handle handle,
- uint32_t number_of_resources,
- amdgpu_bo_handle *resources,
- uint8_t *resource_prios)
+drm_public int amdgpu_bo_list_update(amdgpu_bo_list_handle handle,
+ uint32_t number_of_resources,
+ amdgpu_bo_handle *resources,
+ uint8_t *resource_prios)
{
struct drm_amdgpu_bo_list_entry *list;
union drm_amdgpu_bo_list args;
return r;
}
-int amdgpu_bo_va_op(amdgpu_bo_handle bo,
- uint64_t offset,
- uint64_t size,
- uint64_t addr,
- uint64_t flags,
- uint32_t ops)
+drm_public int amdgpu_bo_va_op(amdgpu_bo_handle bo,
+ uint64_t offset,
+ uint64_t size,
+ uint64_t addr,
+ uint64_t flags,
+ uint32_t ops)
{
amdgpu_device_handle dev = bo->dev;
AMDGPU_VM_PAGE_EXECUTABLE, ops);
}
-int amdgpu_bo_va_op_raw(amdgpu_device_handle dev,
- amdgpu_bo_handle bo,
- uint64_t offset,
- uint64_t size,
- uint64_t addr,
- uint64_t flags,
- uint32_t ops)
+drm_public int amdgpu_bo_va_op_raw(amdgpu_device_handle dev,
+ amdgpu_bo_handle bo,
+ uint64_t offset,
+ uint64_t size,
+ uint64_t addr,
+ uint64_t flags,
+ uint32_t ops)
{
struct drm_amdgpu_gem_va va;
int r;