* IN THE SOFTWARE.
*/
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
#include <assert.h>
#include <stdint.h>
#include <stdlib.h>
#include <stdarg.h>
#include <string.h>
+#include "libdrm_macros.h"
+#include "xf86drm.h"
#include "intel_chipset.h"
#include "intel_bufmgr.h"
+
/* Struct for tracking drm_intel_decode state. */
struct drm_intel_decode {
/** stdio file where the output should land. Defaults to stdout. */
return uval.f;
}
-static void
-instr_out(struct drm_intel_decode *ctx, unsigned int index,
- const char *fmt, ...) __attribute__((format(__printf__, 3, 4)));
-
-static void
+static void DRM_PRINTFLIKE(3, 4)
instr_out(struct drm_intel_decode *ctx, unsigned int index,
const char *fmt, ...)
{
}
static int
+decode_MI_SET_CONTEXT(struct drm_intel_decode *ctx)
+{
+ uint32_t data = ctx->data[1];
+ if (ctx->gen > 7)
+ return 1;
+
+ instr_out(ctx, 0, "MI_SET_CONTEXT\n");
+ instr_out(ctx, 1, "gtt offset = 0x%x%s%s\n",
+ data & ~0xfff,
+ data & (1<<1)? ", Force Restore": "",
+ data & (1<<0)? ", Restore Inhibit": "");
+
+ return 2;
+}
+
+static int
+decode_MI_WAIT_FOR_EVENT(struct drm_intel_decode *ctx)
+{
+ const char *cc_wait;
+ int cc_shift = 0;
+ uint32_t data = ctx->data[0];
+
+ if (ctx->gen <= 5)
+ cc_shift = 9;
+ else
+ cc_shift = 16;
+
+ switch ((data >> cc_shift) & 0x1f) {
+ case 1:
+ cc_wait = ", cc wait 1";
+ break;
+ case 2:
+ cc_wait = ", cc wait 2";
+ break;
+ case 3:
+ cc_wait = ", cc wait 3";
+ break;
+ case 4:
+ cc_wait = ", cc wait 4";
+ break;
+ case 5:
+ cc_wait = ", cc wait 4";
+ break;
+ default:
+ cc_wait = "";
+ break;
+ }
+
+ if (ctx->gen <= 5) {
+ instr_out(ctx, 0, "MI_WAIT_FOR_EVENT%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
+ data & (1<<18)? ", pipe B start vblank wait": "",
+ data & (1<<17)? ", pipe A start vblank wait": "",
+ data & (1<<16)? ", overlay flip pending wait": "",
+ data & (1<<14)? ", pipe B hblank wait": "",
+ data & (1<<13)? ", pipe A hblank wait": "",
+ cc_wait,
+ data & (1<<8)? ", plane C pending flip wait": "",
+ data & (1<<7)? ", pipe B vblank wait": "",
+ data & (1<<6)? ", plane B pending flip wait": "",
+ data & (1<<5)? ", pipe B scan line wait": "",
+ data & (1<<4)? ", fbc idle wait": "",
+ data & (1<<3)? ", pipe A vblank wait": "",
+ data & (1<<2)? ", plane A pending flip wait": "",
+ data & (1<<1)? ", plane A scan line wait": "");
+ } else {
+ instr_out(ctx, 0, "MI_WAIT_FOR_EVENT%s%s%s%s%s%s%s%s%s%s%s%s\n",
+ data & (1<<20)? ", sprite C pending flip wait": "", /* ivb */
+ cc_wait,
+ data & (1<<13)? ", pipe B hblank wait": "",
+ data & (1<<11)? ", pipe B vblank wait": "",
+ data & (1<<10)? ", sprite B pending flip wait": "",
+ data & (1<<9)? ", plane B pending flip wait": "",
+ data & (1<<8)? ", plane B scan line wait": "",
+ data & (1<<5)? ", pipe A hblank wait": "",
+ data & (1<<3)? ", pipe A vblank wait": "",
+ data & (1<<2)? ", sprite A pending flip wait": "",
+ data & (1<<1)? ", plane A pending flip wait": "",
+ data & (1<<0)? ", plane A scan line wait": "");
+ }
+
+ return 1;
+}
+
+static int
decode_mi(struct drm_intel_decode *ctx)
{
unsigned int opcode, len = -1;
unsigned int min_len;
unsigned int max_len;
const char *name;
+ int (*func)(struct drm_intel_decode *ctx);
} opcodes_mi[] = {
{ 0x08, 0, 1, 1, "MI_ARB_ON_OFF" },
{ 0x0a, 0, 1, 1, "MI_BATCH_BUFFER_END" },
{ 0x00, 0, 1, 1, "MI_NOOP" },
{ 0x11, 0x3f, 2, 2, "MI_OVERLAY_FLIP" },
{ 0x07, 0, 1, 1, "MI_REPORT_HEAD" },
- { 0x18, 0x3f, 2, 2, "MI_SET_CONTEXT" },
+ { 0x18, 0x3f, 2, 2, "MI_SET_CONTEXT", decode_MI_SET_CONTEXT },
{ 0x20, 0x3f, 3, 4, "MI_STORE_DATA_IMM" },
{ 0x21, 0x3f, 3, 4, "MI_STORE_DATA_INDEX" },
{ 0x24, 0x3f, 3, 3, "MI_STORE_REGISTER_MEM" },
{ 0x02, 0, 1, 1, "MI_USER_INTERRUPT" },
- { 0x03, 0, 1, 1, "MI_WAIT_FOR_EVENT" },
+ { 0x03, 0, 1, 1, "MI_WAIT_FOR_EVENT", decode_MI_WAIT_FOR_EVENT },
{ 0x16, 0x7f, 3, 3, "MI_SEMAPHORE_MBOX" },
{ 0x26, 0x1f, 3, 4, "MI_FLUSH_DW" },
+ { 0x28, 0x3f, 3, 3, "MI_REPORT_PERF_COUNT" },
+ { 0x29, 0xff, 3, 3, "MI_LOAD_REGISTER_MEM" },
{ 0x0b, 0, 1, 1, "MI_SUSPEND_FLUSH"},
- };
+ }, *opcode_mi = NULL;
/* check instruction length */
for (opcode = 0; opcode < sizeof(opcodes_mi) / sizeof(opcodes_mi[0]);
opcodes_mi[opcode].max_len);
}
}
+ opcode_mi = &opcodes_mi[opcode];
break;
}
}
+ if (opcode_mi && opcode_mi->func)
+ return opcode_mi->func(ctx);
+
switch ((data[0] & 0x1f800000) >> 23) {
case 0x0a:
instr_out(ctx, 0, "MI_BATCH_BUFFER_END\n");
}
} else {
instr_out(ctx, i,
- "S%d: 0x%08x\n", i, data[i]);
+ "S%d: 0x%08x\n", word, data[i]);
}
i++;
}
}
}
-static const char *get_965_prim_type(uint32_t data)
+static const char *get_965_prim_type(uint32_t primtype)
{
- uint32_t primtype = (data >> 10) & 0x1f;
-
switch (primtype) {
case 0x01:
return "point list";
}
static int
+gen7_3DSTATE_HIER_DEPTH_BUFFER(struct drm_intel_decode *ctx)
+{
+ instr_out(ctx, 0, "3DSTATE_HIER_DEPTH_BUFFER\n");
+ instr_out(ctx, 1, "pitch %db\n",
+ (ctx->data[1] & 0x1ffff) + 1);
+ instr_out(ctx, 2, "pointer to HiZ buffer\n");
+
+ return 3;
+}
+
+static int
gen6_3DSTATE_CC_STATE_POINTERS(struct drm_intel_decode *ctx)
{
instr_out(ctx, 0, "3DSTATE_CC_STATE_POINTERS\n");
return gen7_3DSTATE_CONSTANT(ctx, "HS");
}
+
+static int
+gen6_3DSTATE_WM(struct drm_intel_decode *ctx)
+{
+ instr_out(ctx, 0, "3DSTATE_WM\n");
+ instr_out(ctx, 1, "kernel start pointer 0\n");
+ instr_out(ctx, 2,
+ "SPF=%d, VME=%d, Sampler Count %d, "
+ "Binding table count %d\n",
+ (ctx->data[2] >> 31) & 1,
+ (ctx->data[2] >> 30) & 1,
+ (ctx->data[2] >> 27) & 7,
+ (ctx->data[2] >> 18) & 0xff);
+ instr_out(ctx, 3, "scratch offset\n");
+ instr_out(ctx, 4,
+ "Depth Clear %d, Depth Resolve %d, HiZ Resolve %d, "
+ "Dispatch GRF start[0] %d, start[1] %d, start[2] %d\n",
+ (ctx->data[4] & (1 << 30)) != 0,
+ (ctx->data[4] & (1 << 28)) != 0,
+ (ctx->data[4] & (1 << 27)) != 0,
+ (ctx->data[4] >> 16) & 0x7f,
+ (ctx->data[4] >> 8) & 0x7f,
+ (ctx->data[4] & 0x7f));
+ instr_out(ctx, 5,
+ "MaxThreads %d, PS KillPixel %d, PS computed Z %d, "
+ "PS use sourceZ %d, Thread Dispatch %d, PS use sourceW %d, "
+ "Dispatch32 %d, Dispatch16 %d, Dispatch8 %d\n",
+ ((ctx->data[5] >> 25) & 0x7f) + 1,
+ (ctx->data[5] & (1 << 22)) != 0,
+ (ctx->data[5] & (1 << 21)) != 0,
+ (ctx->data[5] & (1 << 20)) != 0,
+ (ctx->data[5] & (1 << 19)) != 0,
+ (ctx->data[5] & (1 << 8)) != 0,
+ (ctx->data[5] & (1 << 2)) != 0,
+ (ctx->data[5] & (1 << 1)) != 0,
+ (ctx->data[5] & (1 << 0)) != 0);
+ instr_out(ctx, 6,
+ "Num SF output %d, Pos XY offset %d, ZW interp mode %d , "
+ "Barycentric interp mode 0x%x, Point raster rule %d, "
+ "Multisample mode %d, "
+ "Multisample Dispatch mode %d\n",
+ (ctx->data[6] >> 20) & 0x3f,
+ (ctx->data[6] >> 18) & 3,
+ (ctx->data[6] >> 16) & 3,
+ (ctx->data[6] >> 10) & 0x3f,
+ (ctx->data[6] & (1 << 9)) != 0,
+ (ctx->data[6] >> 1) & 3,
+ (ctx->data[6] & 1));
+ instr_out(ctx, 7, "kernel start pointer 1\n");
+ instr_out(ctx, 8, "kernel start pointer 2\n");
+
+ return 9;
+}
+
+static int
+gen7_3DSTATE_WM(struct drm_intel_decode *ctx)
+{
+ const char *computed_depth = "";
+ const char *early_depth = "";
+ const char *zw_interp = "";
+
+ switch ((ctx->data[1] >> 23) & 0x3) {
+ case 0:
+ computed_depth = "";
+ break;
+ case 1:
+ computed_depth = "computed depth";
+ break;
+ case 2:
+ computed_depth = "computed depth >=";
+ break;
+ case 3:
+ computed_depth = "computed depth <=";
+ break;
+ }
+
+ switch ((ctx->data[1] >> 21) & 0x3) {
+ case 0:
+ early_depth = "";
+ break;
+ case 1:
+ early_depth = ", EDSC_PSEXEC";
+ break;
+ case 2:
+ early_depth = ", EDSC_PREPS";
+ break;
+ case 3:
+ early_depth = ", BAD EDSC";
+ break;
+ }
+
+ switch ((ctx->data[1] >> 17) & 0x3) {
+ case 0:
+ early_depth = "";
+ break;
+ case 1:
+ early_depth = ", BAD ZW interp";
+ break;
+ case 2:
+ early_depth = ", ZW centroid";
+ break;
+ case 3:
+ early_depth = ", ZW sample";
+ break;
+ }
+
+ instr_out(ctx, 0, "3DSTATE_WM\n");
+ instr_out(ctx, 1, "(%s%s%s%s%s%s)%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
+ (ctx->data[1] & (1 << 11)) ? "PP " : "",
+ (ctx->data[1] & (1 << 12)) ? "PC " : "",
+ (ctx->data[1] & (1 << 13)) ? "PS " : "",
+ (ctx->data[1] & (1 << 14)) ? "NPP " : "",
+ (ctx->data[1] & (1 << 15)) ? "NPC " : "",
+ (ctx->data[1] & (1 << 16)) ? "NPS " : "",
+ (ctx->data[1] & (1 << 30)) ? ", depth clear" : "",
+ (ctx->data[1] & (1 << 29)) ? "" : ", disabled",
+ (ctx->data[1] & (1 << 28)) ? ", depth resolve" : "",
+ (ctx->data[1] & (1 << 27)) ? ", hiz resolve" : "",
+ (ctx->data[1] & (1 << 25)) ? ", kill" : "",
+ computed_depth,
+ early_depth,
+ zw_interp,
+ (ctx->data[1] & (1 << 20)) ? ", source depth" : "",
+ (ctx->data[1] & (1 << 19)) ? ", source W" : "",
+ (ctx->data[1] & (1 << 10)) ? ", coverage" : "",
+ (ctx->data[1] & (1 << 4)) ? ", poly stipple" : "",
+ (ctx->data[1] & (1 << 3)) ? ", line stipple" : "",
+ (ctx->data[1] & (1 << 2)) ? ", point UL" : ", point UR"
+ );
+ instr_out(ctx, 2, "MS\n");
+
+ return 3;
+}
+
+static int
+gen4_3DPRIMITIVE(struct drm_intel_decode *ctx)
+{
+ instr_out(ctx, 0,
+ "3DPRIMITIVE: %s %s\n",
+ get_965_prim_type((ctx->data[0] >> 10) & 0x1f),
+ (ctx->data[0] & (1 << 15)) ? "random" : "sequential");
+ instr_out(ctx, 1, "vertex count\n");
+ instr_out(ctx, 2, "start vertex\n");
+ instr_out(ctx, 3, "instance count\n");
+ instr_out(ctx, 4, "start instance\n");
+ instr_out(ctx, 5, "index bias\n");
+
+ return 6;
+}
+
+static int
+gen7_3DPRIMITIVE(struct drm_intel_decode *ctx)
+{
+ bool indirect = !!(ctx->data[0] & (1 << 10));
+
+ instr_out(ctx, 0,
+ "3DPRIMITIVE: %s%s\n",
+ indirect ? " indirect" : "",
+ (ctx->data[0] & (1 << 8)) ? " predicated" : "");
+ instr_out(ctx, 1, "%s %s\n",
+ get_965_prim_type(ctx->data[1] & 0x3f),
+ (ctx->data[1] & (1 << 8)) ? "random" : "sequential");
+ instr_out(ctx, 2, indirect ? "ignored" : "vertex count\n");
+ instr_out(ctx, 3, indirect ? "ignored" : "start vertex\n");
+ instr_out(ctx, 4, indirect ? "ignored" : "instance count\n");
+ instr_out(ctx, 5, indirect ? "ignored" : "start instance\n");
+ instr_out(ctx, 6, indirect ? "ignored" : "index bias\n");
+
+ return 7;
+}
+
static int
decode_3d_965(struct drm_intel_decode *ctx)
{
{ 0x7805, 0x00ff, 3, 3, "3DSTATE_URB" },
{ 0x7804, 0x00ff, 3, 3, "3DSTATE_CLEAR_PARAMS" },
{ 0x7806, 0x00ff, 3, 3, "3DSTATE_STENCIL_BUFFER" },
- { 0x7807, 0x00ff, 4, 4, "3DSTATE_HIER_DEPTH_BUFFER" },
+ { 0x790f, 0x00ff, 3, 3, "3DSTATE_HIER_DEPTH_BUFFER", 6 },
+ { 0x7807, 0x00ff, 3, 3, "3DSTATE_HIER_DEPTH_BUFFER", 7, gen7_3DSTATE_HIER_DEPTH_BUFFER },
{ 0x7808, 0x00ff, 5, 257, "3DSTATE_VERTEX_BUFFERS" },
{ 0x7809, 0x00ff, 3, 256, "3DSTATE_VERTEX_ELEMENTS" },
{ 0x780a, 0x00ff, 3, 3, "3DSTATE_INDEX_BUFFER" },
{ 0x7812, 0x00ff, 4, 4, "3DSTATE_CLIP" },
{ 0x7813, 0x00ff, 20, 20, "3DSTATE_SF", 6 },
{ 0x7813, 0x00ff, 7, 7, "3DSTATE_SF", 7 },
- { 0x7814, 0x00ff, 3, 3, "3DSTATE_WM", 7 },
- { 0x7814, 0x00ff, 9, 9, "3DSTATE_WM" },
+ { 0x7814, 0x00ff, 3, 3, "3DSTATE_WM", 7, gen7_3DSTATE_WM },
+ { 0x7814, 0x00ff, 9, 9, "3DSTATE_WM", 6, gen6_3DSTATE_WM },
{ 0x7815, 0x00ff, 5, 5, "3DSTATE_CONSTANT_VS_STATE", 6 },
{ 0x7815, 0x00ff, 7, 7, "3DSTATE_CONSTANT_VS", 7, gen7_3DSTATE_CONSTANT_VS },
{ 0x7816, 0x00ff, 5, 5, "3DSTATE_CONSTANT_GS_STATE", 6 },
{ 0x7829, 0x00ff, 2, 2, "3DSTATE_BINDING_TABLE_POINTERS_GS" },
{ 0x782a, 0x00ff, 2, 2, "3DSTATE_BINDING_TABLE_POINTERS_PS" },
{ 0x782b, 0x00ff, 2, 2, "3DSTATE_SAMPLER_STATE_POINTERS_VS" },
+ { 0x782c, 0x00ff, 2, 2, "3DSTATE_SAMPLER_STATE_POINTERS_HS" },
+ { 0x782d, 0x00ff, 2, 2, "3DSTATE_SAMPLER_STATE_POINTERS_DS" },
{ 0x782e, 0x00ff, 2, 2, "3DSTATE_SAMPLER_STATE_POINTERS_GS" },
{ 0x782f, 0x00ff, 2, 2, "3DSTATE_SAMPLER_STATE_POINTERS_PS" },
{ 0x7830, 0x00ff, 2, 2, NULL, 7, gen7_3DSTATE_URB_VS },
{ 0x790b, 0xffff, 4, 4, "3DSTATE_GS_SVB_INDEX" },
{ 0x790d, 0xffff, 3, 3, "3DSTATE_MULTISAMPLE", 6 },
{ 0x790d, 0xffff, 4, 4, "3DSTATE_MULTISAMPLE", 7 },
- { 0x7910, 0xffff, 2, 2, "3DSTATE_CLEAR_PARAMS" },
+ { 0x7910, 0x00ff, 2, 2, "3DSTATE_CLEAR_PARAMS" },
{ 0x7912, 0x00ff, 2, 2, "3DSTATE_PUSH_CONSTANT_ALLOC_VS" },
+ { 0x7913, 0x00ff, 2, 2, "3DSTATE_PUSH_CONSTANT_ALLOC_HS" },
+ { 0x7914, 0x00ff, 2, 2, "3DSTATE_PUSH_CONSTANT_ALLOC_DS" },
+ { 0x7915, 0x00ff, 2, 2, "3DSTATE_PUSH_CONSTANT_ALLOC_GS" },
{ 0x7916, 0x00ff, 2, 2, "3DSTATE_PUSH_CONSTANT_ALLOC_PS" },
{ 0x7917, 0x00ff, 2, 2+128*2, "3DSTATE_SO_DECL_LIST" },
{ 0x7918, 0x00ff, 4, 4, "3DSTATE_SO_BUFFER" },
{ 0x7a00, 0x00ff, 4, 6, "PIPE_CONTROL" },
- { 0x7b00, 0x00ff, 7, 7, "3DPRIMITIVE", 7 },
- { 0x7b00, 0x00ff, 6, 6, "3DPRIMITIVE" },
+ { 0x7b00, 0x00ff, 7, 7, NULL, 7, gen7_3DPRIMITIVE },
+ { 0x7b00, 0x00ff, 6, 6, NULL, 0, gen4_3DPRIMITIVE },
}, *opcode_3d = NULL;
opcode = (data[0] & 0xffff0000) >> 16;
instr_out(ctx, i,
"buffer %d: %svalid, type 0x%04x, "
"src offset 0x%04x bytes\n",
- data[i] >> (IS_GEN6(devid) ? 26 : 27),
- data[i] & (1 << (IS_GEN6(devid) ? 25 : 26)) ?
+ data[i] >> ((IS_GEN6(devid) || IS_GEN7(devid)) ? 26 : 27),
+ data[i] & (1 << ((IS_GEN6(devid) || IS_GEN7(devid)) ? 25 : 26)) ?
"" : "in", (data[i] >> 16) & 0x1ff,
data[i] & 0x07ff);
i++;
return len;
- case 0x7814:
- instr_out(ctx, 0, "3DSTATE_WM\n");
- instr_out(ctx, 1, "kernel start pointer 0\n");
- instr_out(ctx, 2,
- "SPF=%d, VME=%d, Sampler Count %d, "
- "Binding table count %d\n", (data[2] >> 31) & 1,
- (data[2] >> 30) & 1, (data[2] >> 27) & 7,
- (data[2] >> 18) & 0xff);
- instr_out(ctx, 3, "scratch offset\n");
- instr_out(ctx, 4,
- "Depth Clear %d, Depth Resolve %d, HiZ Resolve %d, "
- "Dispatch GRF start[0] %d, start[1] %d, start[2] %d\n",
- (data[4] & (1 << 30)) != 0,
- (data[4] & (1 << 28)) != 0,
- (data[4] & (1 << 27)) != 0, (data[4] >> 16) & 0x7f,
- (data[4] >> 8) & 0x7f, (data[4] & 0x7f));
- instr_out(ctx, 5,
- "MaxThreads %d, PS KillPixel %d, PS computed Z %d, "
- "PS use sourceZ %d, Thread Dispatch %d, PS use sourceW %d, Dispatch32 %d, "
- "Dispatch16 %d, Dispatch8 %d\n",
- ((data[5] >> 25) & 0x7f) + 1,
- (data[5] & (1 << 22)) != 0,
- (data[5] & (1 << 21)) != 0,
- (data[5] & (1 << 20)) != 0,
- (data[5] & (1 << 19)) != 0, (data[5] & (1 << 8)) != 0,
- (data[5] & (1 << 2)) != 0, (data[5] & (1 << 1)) != 0,
- (data[5] & (1 << 0)) != 0);
- instr_out(ctx, 6,
- "Num SF output %d, Pos XY offset %d, ZW interp mode %d , "
- "Barycentric interp mode 0x%x, Point raster rule %d, Multisample mode %d, "
- "Multisample Dispatch mode %d\n",
- (data[6] >> 20) & 0x3f, (data[6] >> 18) & 3,
- (data[6] >> 16) & 3, (data[6] >> 10) & 0x3f,
- (data[6] & (1 << 9)) != 0, (data[6] >> 1) & 3,
- (data[6] & 1));
- instr_out(ctx, 7, "kernel start pointer 1\n");
- instr_out(ctx, 8, "kernel start pointer 2\n");
-
- return len;
-
case 0x7900:
instr_out(ctx, 0, "3DSTATE_DRAWING_RECTANGLE\n");
instr_out(ctx, 1, "top left: %d,%d\n",
instr_out(ctx, 0, "3DSTATE_DEPTH_BUFFER\n");
if (IS_GEN5(devid) || IS_GEN6(devid))
instr_out(ctx, 1,
- "%s, %s, pitch = %d bytes, %stiled, HiZ %d, Seperate Stencil %d\n",
+ "%s, %s, pitch = %d bytes, %stiled, HiZ %d, Separate Stencil %d\n",
get_965_surfacetype(data[1] >> 29),
get_965_depthformat((data[1] >> 18) & 0x7),
(data[1] & 0x0001ffff) + 1,
case 0x7a00:
if (IS_GEN6(devid) || IS_GEN7(devid)) {
- unsigned int i;
if (len != 4 && len != 5)
fprintf(out, "Bad count in PIPE_CONTROL\n");
instr_out(ctx, 3, "immediate dword high\n");
return len;
}
- case 0x7b00:
- if (ctx->gen == 7)
- break;
-
- instr_out(ctx, 0,
- "3DPRIMITIVE: %s %s\n",
- get_965_prim_type(data[0]),
- (data[0] & (1 << 15)) ? "random" : "sequential");
- instr_out(ctx, 1, "vertex count\n");
- instr_out(ctx, 2, "start vertex\n");
- instr_out(ctx, 3, "instance count\n");
- instr_out(ctx, 4, "start instance\n");
- instr_out(ctx, 5, "index bias\n");
- return len;
}
if (opcode_3d) {
if (opcode_3d->func) {
return opcode_3d->func(ctx);
} else {
- unsigned int i;
-
instr_out(ctx, 0, "%s\n", opcode_3d->name);
for (i = 1; i < len; i++) {
ctx->devid = devid;
ctx->out = stdout;
- if (IS_GEN7(devid))
+ if (IS_GEN10(devid))
+ ctx->gen = 10;
+ else if (IS_GEN9(devid))
+ ctx->gen = 9;
+ else if (IS_GEN8(devid))
+ ctx->gen = 8;
+ else if (IS_GEN7(devid))
ctx->gen = 7;
else if (IS_GEN6(devid))
ctx->gen = 6;
void
drm_intel_decode_set_output_file(struct drm_intel_decode *ctx,
- FILE *out)
+ FILE *output)
{
- ctx->out = out;
+ ctx->out = output;
}
/**
int ret;
unsigned int index = 0;
uint32_t devid;
- int size = ctx->base_count * 4;
+ int size;
void *temp;
if (!ctx)
* the batchbuffer. This lets us avoid a bunch of length
* checking in statically sized packets.
*/
+ size = ctx->base_count * 4;
temp = malloc(size + 4096);
memcpy(temp, ctx->base_data, size);
memset((char *)temp + size, 0xd0, 4096);
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