functionality, or simply have a lot to talk about), see the `NOTE` below
for adding a new subsection.
+* The Windows installer no longer includes a Visual Studio integration.
+ Instead, a new
+ `LLVM Compiler Toolchain Visual Studio extension <https://marketplace.visualstudio.com/items?itemName=LLVMExtensions.llvm-toolchain>`
+ is available on the Visual Studio Marketplace. The new integration includes
+ support for Visual Studio 2017.
+
+* Libraries have been renamed from 7.0 to 7. This change also impacts
+ downstream libraries like lldb.
+
* The LoopInstSimplify pass (-loop-instsimplify) has been removed.
* Symbols starting with ``?`` are no longer mangled by LLVM when using the
Windows ``x`` or ``w`` IR mangling schemes.
+* A new tool named :doc:`llvm-exegesis <CommandGuide/llvm-exegesis>` has been
+ added. :program:`llvm-exegesis` automatically measures instruction scheduling
+ properties (latency/uops) and provides a principled way to edit scheduling
+ models.
+
+* A new tool named :doc:`llvm-mca <CommandGuide/llvm-mca>` has been added.
+ :program:`llvm-mca` is a static performance analysis tool that uses
+ information available in LLVM to statically predict the performance of
+ machine code for a specific CPU.
+
+* The optimization flag to merge constants (-fmerge-all-constants) is no longer
+ applied by default.
+
+* Optimization of floating-point casts is improved. This may cause surprising
+ results for code that is relying on the undefined behavior of overflowing
+ casts. The optimization can be disabled by specifying a function attribute:
+ "strict-float-cast-overflow"="false". This attribute may be created by the
+ clang option ``-fno-strict-float-cast-overflow``.
+ Code sanitizers can be used to detect affected patterns. The option for
+ detecting this problem alone is "-fsanitize=float-cast-overflow":
+
+.. code-block:: c
+
+ int main() {
+ float x = 4294967296.0f;
+ x = (float)((int)x);
+ printf("junk in the ftrunc: %f\n", x);
+ return 0;
+ }
+
+.. code-block:: bash
+
+ clang -O1 ftrunc.c -fsanitize=float-cast-overflow ; ./a.out
+ ftrunc.c:5:15: runtime error: 4.29497e+09 is outside the range of representable values of type 'int'
+ junk in the ftrunc: 0.000000
+
+* ``LLVM_ON_WIN32`` is no longer set by ``llvm/Config/config.h`` and
+ ``llvm/Config/llvm-config.h``. If you used this macro, use the compiler-set
+ ``_WIN32`` instead which is set exactly when ``LLVM_ON_WIN32`` used to be set.
+
+* The ``DEBUG`` macro has been renamed to ``LLVM_DEBUG``, the interface remains
+ the same. If you used this macro you need to migrate to the new one.
+ You should also clang-format your code to make it easier to integrate future
+ changes locally. This can be done with the following bash commands:
+
+.. code-block:: bash
+
+ git grep -l 'DEBUG' | xargs perl -pi -e 's/\bDEBUG\s?\(/LLVM_DEBUG(/g'
+ git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM
+
+* Early support for UBsan, X-Ray instrumentation and libFuzzer (x86 and x86_64) for OpenBSD. Support for MSan
+ (x86_64), X-Ray instrumentation and libFuzzer (x86 and x86_64) for FreeBSD.
+
+* ``SmallVector<T, 0>`` shrank from ``sizeof(void*) * 4 + sizeof(T)`` to
+ ``sizeof(void*) + sizeof(unsigned) * 2``, smaller than ``std::vector<T>`` on
+ 64-bit platforms. The maximum capacity is now restricted to ``UINT32_MAX``.
+ Since SmallVector doesn't have the exception-safety pessimizations some
+ implementations saddle std::vector with and is better at using ``realloc``,
+ it's now a better choice even on the heap (although when TinyPtrVector works,
+ it's even smaller).
+
+* Preliminary/experimental support for DWARF v5 debugging information,
+ including the new .debug_names accelerator table. DWARF emitted at ``-O0``
+ should be fully DWARF v5 compliant. Type units and split DWARF are known
+ not to be compliant, and higher optimization levels will still emit some
+ information in v4 format.
+
+* Added support for the ``.rva`` assembler directive for COFF targets.
+
+* The :program:`llvm-rc` tool (Windows Resource Compiler) has been improved
+ a bit. There are still known missing features, but it is generally usable
+ in many cases. (The tool still doesn't preprocess input files automatically,
+ but it can now handle leftover C declarations in preprocessor output, if
+ given output from a preprocessor run externally.)
+
+* CodeView debug info can now be emitted MinGW configurations, if requested.
+
* Note..
.. NOTE
have changed. Alignment is no longer an argument, and are instead conveyed as
parameter attributes.
-Changes to the ARM Backend
---------------------------
+* invariant.group.barrier has been renamed to launder.invariant.group.
- During this release ...
+* invariant.group metadata can now refer only empty metadata nodes.
+
+Changes to the AArch64 Target
+-----------------------------
+
+* The ``.inst`` assembler directive is now usable on both COFF and Mach-O
+ targets, in addition to ELF.
+
+* Support for most remaining COFF relocations have been added.
+
+* Support for TLS on Windows has been added.
+
+Changes to the ARM Target
+-------------------------
+
+* The ``.inst`` assembler directive is now usable on both COFF and Mach-O
+ targets, in addition to ELF. For Thumb, it can now also automatically
+ deduce the instruction size, without having to specify it with
+ e.g. ``.inst.w`` as before.
+
+Changes to the Hexagon Target
+-----------------------------
+* Hexagon now supports auto-vectorization for HVX. It is disabled by default
+ and can be turned on with ``-fvectorize``. For auto-vectorization to take
+ effect, code generation for HVX needs to be enabled with ``-mhvx``.
+ The complete set of options should include ``-fvectorize``, ``-mhvx``,
+ and ``-mhvx-length={64b|128b}``.
+
+* The support for Hexagon ISA V4 is deprecated and will be removed in the
+ next release.
Changes to the MIPS Target
--------------------------
- During this release ...
+During this release the MIPS target has:
+
+* Added support for Virtualization, Global INValidate ASE,
+ and CRC ASE instructions.
+
+* Introduced definitions of ``[d]rem``, ``[d]remu``,
+ and microMIPSR6 ``ll/sc`` instructions.
+
+* Shrink-wrapping is now supported and enabled by default (except for -O0).
+
+* Extended size reduction pass by the LWP and SWP instructions.
+
+* Gained initial support of GlobalISel instruction selection framework.
+
+* Updated the P5600 scheduler model not to use instruction itineraries.
+
+* Added disassembly support for comparison and fused (negative) multiply
+ ``add/sub`` instructions.
+
+* Improved the selection of multiple instructions.
+
+* Load/store lb, sb, ld, sd, lld, ... instructions
+ now support 32/64-bit offsets.
+
+* Added support for ``y``, ``M``, and ``L`` inline assembler operand codes.
+
+* Extended list of relocations supported by the ``.reloc`` directive
+
+* Fixed using a wrong register class for creating an emergency
+ spill slot for mips3 / n64 abi.
+
+* MIPS relocation types were generated for microMIPS code.
+
+* Corrected definitions of multiple instructions (``lwp``, ``swp``, ``ctc2``,
+ ``cfc2``, ``sync``, ``synci``, ``cvt.d.w``, ...).
+* Fixed atomic operations at O0 level.
+
+* Fixed local dynamic TLS with Sym64
Changes to the PowerPC Target
-----------------------------
During this release ...
+Changes to the SystemZ Target
+-----------------------------
+
+During this release the SystemZ target has:
+
+* Added support for vector registers in inline asm statements.
+
+* Added support for stackmaps, patchpoints, and the anyregcc
+ calling convention.
+
+* Changed the default function alignment to 16 bytes.
+
+* Improved codegen for condition code handling.
+
+* Improved instruction scheduling and microarchitecture tuning for z13/z14.
+
+* Fixed support for generating GCOV coverage data.
+
+* Fixed some codegen bugs.
+
Changes to the X86 Target
-------------------------
- During this release ...
+* The calling convention for the ``f80`` data type on MinGW targets has been
+ fixed. Normally, the calling convention for this type is handled within clang,
+ but if an intrinsic is used, which LLVM expands into a libcall, the
+ proper calling convention needs to be supported in LLVM as well. (Note,
+ on Windows, this data type is only used for long doubles in MinGW
+ environments - in MSVC environments, long doubles are the same size as
+ normal doubles.)
Changes to the AMDGPU Target
-----------------------------
Changes to the OCaml bindings
-----------------------------
- During this release ...
+* Remove ``add_bb_vectorize``.
Changes to the C API
--------------------
- During this release ...
+* Remove ``LLVMAddBBVectorizePass``. The implementation was removed and the C
+ interface was made a deprecated no-op in LLVM 5. Use
+ ``LLVMAddSLPVectorizePass`` instead to get the supported SLP vectorizer.
+
+Changes to the DAG infrastructure
+---------------------------------
+* ADDC/ADDE/SUBC/SUBE are now deprecated and will default to expand. Backends
+ that wish to continue to use these opcodes should explicitely request so
+ using ``setOperationAction`` in their ``TargetLowering``. New backends
+ should use UADDO/ADDCARRY/USUBO/SUBCARRY instead of the deprecated opcodes.
+
+* The SETCCE opcode has now been removed in favor of SETCCCARRY.
+* TableGen now supports multi-alternative pattern fragments via the PatFrags
+ class. PatFrag is now derived from PatFrags, which may require minor
+ changes to backends that directly access PatFrag members.
External Open Source Projects Using LLVM 7
==========================================
OSDN Git Service
