#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/FileSystem.h"
+#include "llvm/Support/Format.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
MachineVerifier(Pass *pass, const char *b) :
PASS(pass),
- Banner(b),
- OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
+ Banner(b)
{}
bool runOnMachineFunction(MachineFunction &MF);
Pass *const PASS;
const char *Banner;
- const char *const OutFileName;
- raw_ostream *OS;
const MachineFunction *MF;
const TargetMachine *TM;
const TargetInstrInfo *TII;
void report(const char *msg, const MachineBasicBlock *MBB,
const LiveInterval &LI);
void report(const char *msg, const MachineFunction *MF,
- const LiveRange &LR, unsigned Reg);
+ const LiveRange &LR, unsigned Reg, unsigned LaneMask);
void report(const char *msg, const MachineBasicBlock *MBB,
- const LiveRange &LR, unsigned Reg);
+ const LiveRange &LR, unsigned Reg, unsigned LaneMask);
void verifyInlineAsm(const MachineInstr *MI);
void verifyLiveVariables();
void verifyLiveIntervals();
void verifyLiveInterval(const LiveInterval&);
- void verifyLiveRangeValue(const LiveRange&, const VNInfo*, unsigned);
+ void verifyLiveRangeValue(const LiveRange&, const VNInfo*, unsigned,
+ unsigned);
void verifyLiveRangeSegment(const LiveRange&,
- const LiveRange::const_iterator I, unsigned);
- void verifyLiveRange(const LiveRange&, unsigned);
+ const LiveRange::const_iterator I, unsigned,
+ unsigned);
+ void verifyLiveRange(const LiveRange&, unsigned, unsigned LaneMask = 0);
void verifyStackFrame();
};
struct MachineVerifierPass : public MachineFunctionPass {
static char ID; // Pass ID, replacement for typeid
- const char *const Banner;
+ const std::string Banner;
- MachineVerifierPass(const char *b = nullptr)
- : MachineFunctionPass(ID), Banner(b) {
+ MachineVerifierPass(const std::string &banner = nullptr)
+ : MachineFunctionPass(ID), Banner(banner) {
initializeMachineVerifierPassPass(*PassRegistry::getPassRegistry());
}
}
bool runOnMachineFunction(MachineFunction &MF) override {
- MF.verify(this, Banner);
+ MF.verify(this, Banner.c_str());
return false;
}
};
INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
"Verify generated machine code", false, false)
-FunctionPass *llvm::createMachineVerifierPass(const char *Banner) {
+FunctionPass *llvm::createMachineVerifierPass(const std::string &Banner) {
return new MachineVerifierPass(Banner);
}
}
bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
- raw_ostream *OutFile = nullptr;
- if (OutFileName) {
- std::error_code EC;
- OutFile = new raw_fd_ostream(OutFileName, EC,
- sys::fs::F_Append | sys::fs::F_Text);
- if (EC) {
- errs() << "Error opening '" << OutFileName << "': " << EC.message()
- << '\n';
- exit(1);
- }
-
- OS = OutFile;
- } else {
- OS = &errs();
- }
-
foundErrors = 0;
this->MF = &MF;
MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI) {
if (MBBI->getParent() != MFI) {
report("Bad instruction parent pointer", MFI);
- *OS << "Instruction: " << *MBBI;
+ errs() << "Instruction: " << *MBBI;
continue;
}
}
visitMachineFunctionAfter();
- if (OutFile)
- delete OutFile;
- else if (foundErrors)
+ if (foundErrors)
report_fatal_error("Found "+Twine(foundErrors)+" machine code errors.");
// Clean up.
void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
assert(MF);
- *OS << '\n';
+ errs() << '\n';
if (!foundErrors++) {
if (Banner)
- *OS << "# " << Banner << '\n';
- MF->print(*OS, Indexes);
+ errs() << "# " << Banner << '\n';
+ MF->print(errs(), Indexes);
}
- *OS << "*** Bad machine code: " << msg << " ***\n"
+ errs() << "*** Bad machine code: " << msg << " ***\n"
<< "- function: " << MF->getName() << "\n";
}
void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
assert(MBB);
report(msg, MBB->getParent());
- *OS << "- basic block: BB#" << MBB->getNumber()
+ errs() << "- basic block: BB#" << MBB->getNumber()
<< ' ' << MBB->getName()
<< " (" << (const void*)MBB << ')';
if (Indexes)
- *OS << " [" << Indexes->getMBBStartIdx(MBB)
+ errs() << " [" << Indexes->getMBBStartIdx(MBB)
<< ';' << Indexes->getMBBEndIdx(MBB) << ')';
- *OS << '\n';
+ errs() << '\n';
}
void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
assert(MI);
report(msg, MI->getParent());
- *OS << "- instruction: ";
+ errs() << "- instruction: ";
if (Indexes && Indexes->hasIndex(MI))
- *OS << Indexes->getInstructionIndex(MI) << '\t';
- MI->print(*OS, TM);
+ errs() << Indexes->getInstructionIndex(MI) << '\t';
+ MI->print(errs(), TM);
}
void MachineVerifier::report(const char *msg,
const MachineOperand *MO, unsigned MONum) {
assert(MO);
report(msg, MO->getParent());
- *OS << "- operand " << MONum << ": ";
- MO->print(*OS, TM);
- *OS << "\n";
+ errs() << "- operand " << MONum << ": ";
+ MO->print(errs(), TM);
+ errs() << "\n";
}
void MachineVerifier::report(const char *msg, const MachineFunction *MF,
const LiveInterval &LI) {
report(msg, MF);
- *OS << "- interval: " << LI << '\n';
+ errs() << "- interval: " << LI << '\n';
}
void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB,
const LiveInterval &LI) {
report(msg, MBB);
- *OS << "- interval: " << LI << '\n';
+ errs() << "- interval: " << LI << '\n';
}
void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB,
- const LiveRange &LR, unsigned Reg) {
+ const LiveRange &LR, unsigned Reg,
+ unsigned LaneMask) {
report(msg, MBB);
- *OS << "- liverange: " << LR << '\n';
- *OS << "- register: " << PrintReg(Reg, TRI) << '\n';
+ errs() << "- liverange: " << LR << '\n';
+ errs() << "- register: " << PrintReg(Reg, TRI) << '\n';
+ if (LaneMask != 0)
+ errs() << "- lanemask: " << format("%04X\n", LaneMask);
}
void MachineVerifier::report(const char *msg, const MachineFunction *MF,
- const LiveRange &LR, unsigned Reg) {
+ const LiveRange &LR, unsigned Reg,
+ unsigned LaneMask) {
report(msg, MF);
- *OS << "- liverange: " << LR << '\n';
- *OS << "- register: " << PrintReg(Reg, TRI) << '\n';
+ errs() << "- liverange: " << LR << '\n';
+ errs() << "- register: " << PrintReg(Reg, TRI) << '\n';
+ if (LaneMask != 0)
+ errs() << "- lanemask: " << format("%04X\n", LaneMask);
}
void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
report("MBB has successor that isn't part of the function.", MBB);
if (!MBBInfoMap[*I].Preds.count(MBB)) {
report("Inconsistent CFG", MBB);
- *OS << "MBB is not in the predecessor list of the successor BB#"
+ errs() << "MBB is not in the predecessor list of the successor BB#"
<< (*I)->getNumber() << ".\n";
}
}
report("MBB has predecessor that isn't part of the function.", MBB);
if (!MBBInfoMap[*I].Succs.count(MBB)) {
report("Inconsistent CFG", MBB);
- *OS << "MBB is not in the successor list of the predecessor BB#"
+ errs() << "MBB is not in the successor list of the predecessor BB#"
<< (*I)->getNumber() << ".\n";
}
}
}
} else if (TBB && !FBB && Cond.empty()) {
// Block unconditionally branches somewhere.
- if (MBB->succ_size() != 1+LandingPadSuccs.size()) {
+ // If the block has exactly one successor, that happens to be a
+ // landingpad, accept it as valid control flow.
+ if (MBB->succ_size() != 1+LandingPadSuccs.size() &&
+ (MBB->succ_size() != 1 || LandingPadSuccs.size() != 1 ||
+ *MBB->succ_begin() != *LandingPadSuccs.begin())) {
report("MBB exits via unconditional branch but doesn't have "
"exactly one CFG successor!", MBB);
} else if (!MBB->isSuccessor(TBB)) {
SlotIndex idx = Indexes->getInstructionIndex(MI);
if (!(idx > lastIndex)) {
report("Instruction index out of order", MI);
- *OS << "Last instruction was at " << lastIndex << '\n';
+ errs() << "Last instruction was at " << lastIndex << '\n';
}
lastIndex = idx;
}
FirstTerminator = MI;
} else if (FirstTerminator) {
report("Non-terminator instruction after the first terminator", MI);
- *OS << "First terminator was:\t" << *FirstTerminator;
+ errs() << "First terminator was:\t" << *FirstTerminator;
}
}
const MCInstrDesc &MCID = MI->getDesc();
if (MI->getNumOperands() < MCID.getNumOperands()) {
report("Too few operands", MI);
- *OS << MCID.getNumOperands() << " operands expected, but "
+ errs() << MCID.getNumOperands() << " operands expected, but "
<< MI->getNumOperands() << " given.\n";
}
TII->getRegClass(MCID, MONum, TRI, *MF)) {
if (!DRC->contains(Reg)) {
report("Illegal physical register for instruction", MO, MONum);
- *OS << TRI->getName(Reg) << " is not a "
+ errs() << TRI->getName(Reg) << " is not a "
<< TRI->getRegClassName(DRC) << " register.\n";
}
}
TRI->getSubClassWithSubReg(RC, SubIdx);
if (!SRC) {
report("Invalid subregister index for virtual register", MO, MONum);
- *OS << "Register class " << TRI->getRegClassName(RC)
+ errs() << "Register class " << TRI->getRegClassName(RC)
<< " does not support subreg index " << SubIdx << "\n";
return;
}
if (RC != SRC) {
report("Invalid register class for subregister index", MO, MONum);
- *OS << "Register class " << TRI->getRegClassName(RC)
+ errs() << "Register class " << TRI->getRegClassName(RC)
<< " does not fully support subreg index " << SubIdx << "\n";
return;
}
}
if (!RC->hasSuperClassEq(DRC)) {
report("Illegal virtual register for instruction", MO, MONum);
- *OS << "Expected a " << TRI->getRegClassName(DRC)
+ errs() << "Expected a " << TRI->getRegClassName(DRC)
<< " register, but got a " << TRI->getRegClassName(RC)
<< " register\n";
}
SlotIndex Idx = LiveInts->getInstructionIndex(MI);
if (MI->mayLoad() && !LI.liveAt(Idx.getRegSlot(true))) {
report("Instruction loads from dead spill slot", MO, MONum);
- *OS << "Live stack: " << LI << '\n';
+ errs() << "Live stack: " << LI << '\n';
}
if (MI->mayStore() && !LI.liveAt(Idx.getRegSlot())) {
report("Instruction stores to dead spill slot", MO, MONum);
- *OS << "Live stack: " << LI << '\n';
+ errs() << "Live stack: " << LI << '\n';
}
}
break;
LiveQueryResult LRQ = LR->Query(UseIdx);
if (!LRQ.valueIn()) {
report("No live segment at use", MO, MONum);
- *OS << UseIdx << " is not live in " << PrintRegUnit(*Units, TRI)
+ errs() << UseIdx << " is not live in " << PrintRegUnit(*Units, TRI)
<< ' ' << *LR << '\n';
}
if (MO->isKill() && !LRQ.isKill()) {
report("Live range continues after kill flag", MO, MONum);
- *OS << PrintRegUnit(*Units, TRI) << ' ' << *LR << '\n';
+ errs() << PrintRegUnit(*Units, TRI) << ' ' << *LR << '\n';
}
}
}
LiveQueryResult LRQ = LI.Query(UseIdx);
if (!LRQ.valueIn()) {
report("No live segment at use", MO, MONum);
- *OS << UseIdx << " is not live in " << LI << '\n';
+ errs() << UseIdx << " is not live in " << LI << '\n';
}
// Check for extra kill flags.
// Note that we allow missing kill flags for now.
if (MO->isKill() && !LRQ.isKill()) {
report("Live range continues after kill flag", MO, MONum);
- *OS << "Live range: " << LI << '\n';
+ errs() << "Live range: " << LI << '\n';
}
} else {
report("Virtual register has no live interval", MO, MONum);
if (!regsLive.count(Reg)) {
if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
// Reserved registers may be used even when 'dead'.
- if (!isReserved(Reg))
+ bool Bad = !isReserved(Reg);
+ // We are fine if just any subregister has a defined value.
+ if (Bad) {
+ for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid();
+ ++SubRegs) {
+ if (regsLive.count(*SubRegs)) {
+ Bad = false;
+ break;
+ }
+ }
+ }
+ // If there is an additional implicit-use of a super register we stop
+ // here. By definition we are fine if the super register is not
+ // (completely) dead, if the complete super register is dead we will
+ // get a report for its operand.
+ if (Bad) {
+ for (const MachineOperand &MOP : MI->uses()) {
+ if (!MOP.isReg())
+ continue;
+ if (!MOP.isImplicit())
+ continue;
+ for (MCSubRegIterator SubRegs(MOP.getReg(), TRI); SubRegs.isValid();
+ ++SubRegs) {
+ if (*SubRegs == Reg) {
+ Bad = false;
+ break;
+ }
+ }
+ }
+ }
+ if (Bad)
report("Using an undefined physical register", MO, MONum);
} else if (MRI->def_empty(Reg)) {
report("Reading virtual register without a def", MO, MONum);
assert(VNI && "NULL valno is not allowed");
if (VNI->def != DefIdx) {
report("Inconsistent valno->def", MO, MONum);
- *OS << "Valno " << VNI->id << " is not defined at "
+ errs() << "Valno " << VNI->id << " is not defined at "
<< DefIdx << " in " << LI << '\n';
}
} else {
report("No live segment at def", MO, MONum);
- *OS << DefIdx << " is not live in " << LI << '\n';
+ errs() << DefIdx << " is not live in " << LI << '\n';
}
// Check that, if the dead def flag is present, LiveInts agree.
if (MO->isDead()) {
LiveQueryResult LRQ = LI.Query(DefIdx);
if (!LRQ.isDeadDef()) {
report("Live range continues after dead def flag", MO, MONum);
- *OS << "Live range: " << LI << '\n';
+ errs() << "Live range: " << LI << '\n';
}
}
} else {
SlotIndex stop = Indexes->getMBBEndIdx(MBB);
if (!(stop > lastIndex)) {
report("Block ends before last instruction index", MBB);
- *OS << "Block ends at " << stop
+ errs() << "Block ends at " << stop
<< " last instruction was at " << lastIndex << '\n';
}
lastIndex = stop;
PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
if (!seen.count(*PrI)) {
report("Missing PHI operand", &BBI);
- *OS << "BB#" << (*PrI)->getNumber()
+ errs() << "BB#" << (*PrI)->getNumber()
<< " is a predecessor according to the CFG.\n";
}
}
++I)
if (MInfo.regsKilled.count(*I)) {
report("Virtual register killed in block, but needed live out.", &MBB);
- *OS << "Virtual register " << PrintReg(*I)
+ errs() << "Virtual register " << PrintReg(*I)
<< " is used after the block.\n";
}
}
if (MInfo.vregsRequired.count(Reg)) {
if (!VI.AliveBlocks.test(MBB.getNumber())) {
report("LiveVariables: Block missing from AliveBlocks", &MBB);
- *OS << "Virtual register " << PrintReg(Reg)
+ errs() << "Virtual register " << PrintReg(Reg)
<< " must be live through the block.\n";
}
} else {
if (VI.AliveBlocks.test(MBB.getNumber())) {
report("LiveVariables: Block should not be in AliveBlocks", &MBB);
- *OS << "Virtual register " << PrintReg(Reg)
+ errs() << "Virtual register " << PrintReg(Reg)
<< " is not needed live through the block.\n";
}
}
if (!LiveInts->hasInterval(Reg)) {
report("Missing live interval for virtual register", MF);
- *OS << PrintReg(Reg, TRI) << " still has defs or uses\n";
+ errs() << PrintReg(Reg, TRI) << " still has defs or uses\n";
continue;
}
}
void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
- const VNInfo *VNI,
- unsigned Reg) {
+ const VNInfo *VNI, unsigned Reg,
+ unsigned LaneMask) {
if (VNI->isUnused())
return;
const VNInfo *DefVNI = LR.getVNInfoAt(VNI->def);
if (!DefVNI) {
- report("Valno not live at def and not marked unused", MF, LR, Reg);
- *OS << "Valno #" << VNI->id << '\n';
+ report("Valno not live at def and not marked unused", MF, LR, Reg,
+ LaneMask);
+ errs() << "Valno #" << VNI->id << '\n';
return;
}
if (DefVNI != VNI) {
- report("Live segment at def has different valno", MF, LR, Reg);
- *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
+ report("Live segment at def has different valno", MF, LR, Reg, LaneMask);
+ errs() << "Valno #" << VNI->id << " is defined at " << VNI->def
<< " where valno #" << DefVNI->id << " is live\n";
return;
}
const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
if (!MBB) {
- report("Invalid definition index", MF, LR, Reg);
- *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
+ report("Invalid definition index", MF, LR, Reg, LaneMask);
+ errs() << "Valno #" << VNI->id << " is defined at " << VNI->def
<< " in " << LR << '\n';
return;
}
if (VNI->isPHIDef()) {
if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
- report("PHIDef value is not defined at MBB start", MBB, LR, Reg);
- *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
+ report("PHIDef value is not defined at MBB start", MBB, LR, Reg,
+ LaneMask);
+ errs() << "Valno #" << VNI->id << " is defined at " << VNI->def
<< ", not at the beginning of BB#" << MBB->getNumber() << '\n';
}
return;
// Non-PHI def.
const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
if (!MI) {
- report("No instruction at def index", MBB, LR, Reg);
- *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
+ report("No instruction at def index", MBB, LR, Reg, LaneMask);
+ errs() << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
return;
}
!TRI->hasRegUnit(MOI->getReg(), Reg))
continue;
}
+ if (LaneMask != 0 &&
+ (TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask) == 0)
+ continue;
hasDef = true;
if (MOI->isEarlyClobber())
isEarlyClobber = true;
if (!hasDef) {
report("Defining instruction does not modify register", MI);
- *OS << "Valno #" << VNI->id << " in " << LR << '\n';
+ errs() << "Valno #" << VNI->id << " in " << LR << '\n';
}
// Early clobber defs begin at USE slots, but other defs must begin at
if (isEarlyClobber) {
if (!VNI->def.isEarlyClobber()) {
report("Early clobber def must be at an early-clobber slot", MBB, LR,
- Reg);
- *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
+ Reg, LaneMask);
+ errs() << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
}
} else if (!VNI->def.isRegister()) {
report("Non-PHI, non-early clobber def must be at a register slot",
- MBB, LR, Reg);
- *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
+ MBB, LR, Reg, LaneMask);
+ errs() << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
}
}
}
void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
const LiveRange::const_iterator I,
- unsigned Reg) {
+ unsigned Reg, unsigned LaneMask) {
const LiveRange::Segment &S = *I;
const VNInfo *VNI = S.valno;
assert(VNI && "Live segment has no valno");
if (VNI->id >= LR.getNumValNums() || VNI != LR.getValNumInfo(VNI->id)) {
- report("Foreign valno in live segment", MF, LR, Reg);
- *OS << S << " has a bad valno\n";
+ report("Foreign valno in live segment", MF, LR, Reg, LaneMask);
+ errs() << S << " has a bad valno\n";
}
if (VNI->isUnused()) {
- report("Live segment valno is marked unused", MF, LR, Reg);
- *OS << S << '\n';
+ report("Live segment valno is marked unused", MF, LR, Reg, LaneMask);
+ errs() << S << '\n';
}
const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(S.start);
if (!MBB) {
- report("Bad start of live segment, no basic block", MF, LR, Reg);
- *OS << S << '\n';
+ report("Bad start of live segment, no basic block", MF, LR, Reg, LaneMask);
+ errs() << S << '\n';
return;
}
SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
if (S.start != MBBStartIdx && S.start != VNI->def) {
- report("Live segment must begin at MBB entry or valno def", MBB, LR, Reg);
- *OS << S << '\n';
+ report("Live segment must begin at MBB entry or valno def", MBB, LR, Reg,
+ LaneMask);
+ errs() << S << '\n';
}
const MachineBasicBlock *EndMBB =
LiveInts->getMBBFromIndex(S.end.getPrevSlot());
if (!EndMBB) {
- report("Bad end of live segment, no basic block", MF, LR, Reg);
- *OS << S << '\n';
+ report("Bad end of live segment, no basic block", MF, LR, Reg, LaneMask);
+ errs() << S << '\n';
return;
}
const MachineInstr *MI =
LiveInts->getInstructionFromIndex(S.end.getPrevSlot());
if (!MI) {
- report("Live segment doesn't end at a valid instruction", EndMBB, LR, Reg);
- *OS << S << '\n';
+ report("Live segment doesn't end at a valid instruction", EndMBB, LR, Reg,
+ LaneMask);
+ errs() << S << '\n';
return;
}
// The block slot must refer to a basic block boundary.
if (S.end.isBlock()) {
- report("Live segment ends at B slot of an instruction", EndMBB, LR, Reg);
- *OS << S << '\n';
+ report("Live segment ends at B slot of an instruction", EndMBB, LR, Reg,
+ LaneMask);
+ errs() << S << '\n';
}
if (S.end.isDead()) {
// That means there must be a dead def.
if (!SlotIndex::isSameInstr(S.start, S.end)) {
report("Live segment ending at dead slot spans instructions", EndMBB, LR,
- Reg);
- *OS << S << '\n';
+ Reg, LaneMask);
+ errs() << S << '\n';
}
}
if (S.end.isEarlyClobber()) {
if (I+1 == LR.end() || (I+1)->start != S.end) {
report("Live segment ending at early clobber slot must be "
- "redefined by an EC def in the same instruction", EndMBB, LR, Reg);
- *OS << S << '\n';
+ "redefined by an EC def in the same instruction", EndMBB, LR, Reg,
+ LaneMask);
+ errs() << S << '\n';
}
}
// A live segment can end with either a redefinition, a kill flag on a
// use, or a dead flag on a def.
bool hasRead = false;
+ bool hasSubRegDef = false;
for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) {
if (!MOI->isReg() || MOI->getReg() != Reg)
continue;
+ if (LaneMask != 0 &&
+ (LaneMask & TRI->getSubRegIndexLaneMask(MOI->getSubReg())) == 0)
+ continue;
+ if (MOI->isDef() && MOI->getSubReg() != 0)
+ hasSubRegDef = true;
if (MOI->readsReg())
hasRead = true;
}
if (!S.end.isDead()) {
if (!hasRead) {
- report("Instruction ending live segment doesn't read the register", MI);
- *OS << S << " in " << LR << '\n';
+ // When tracking subregister liveness, the main range must start new
+ // values on partial register writes, even if there is no read.
+ if (!MRI->tracksSubRegLiveness() || LaneMask != 0 || !hasSubRegDef) {
+ report("Instruction ending live segment doesn't read the register",
+ MI);
+ errs() << S << " in " << LR << '\n';
+ }
}
}
}
// All predecessors must have a live-out value.
if (!PVNI) {
- report("Register not marked live out of predecessor", *PI, LR, Reg);
- *OS << "Valno #" << VNI->id << " live into BB#" << MFI->getNumber()
+ report("Register not marked live out of predecessor", *PI, LR, Reg,
+ LaneMask);
+ errs() << "Valno #" << VNI->id << " live into BB#" << MFI->getNumber()
<< '@' << LiveInts->getMBBStartIdx(MFI) << ", not live before "
<< PEnd << '\n';
continue;
// Only PHI-defs can take different predecessor values.
if (!IsPHI && PVNI != VNI) {
- report("Different value live out of predecessor", *PI, LR, Reg);
- *OS << "Valno #" << PVNI->id << " live out of BB#"
+ report("Different value live out of predecessor", *PI, LR, Reg,
+ LaneMask);
+ errs() << "Valno #" << PVNI->id << " live out of BB#"
<< (*PI)->getNumber() << '@' << PEnd
<< "\nValno #" << VNI->id << " live into BB#" << MFI->getNumber()
<< '@' << LiveInts->getMBBStartIdx(MFI) << '\n';
}
}
-void MachineVerifier::verifyLiveRange(const LiveRange &LR, unsigned Reg) {
- for (LiveRange::const_vni_iterator I = LR.vni_begin(), E = LR.vni_end();
- I != E; ++I)
- verifyLiveRangeValue(LR, *I, Reg);
+void MachineVerifier::verifyLiveRange(const LiveRange &LR, unsigned Reg,
+ unsigned LaneMask) {
+ for (const VNInfo *VNI : LR.valnos)
+ verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
for (LiveRange::const_iterator I = LR.begin(), E = LR.end(); I != E; ++I)
- verifyLiveRangeSegment(LR, I, Reg);
+ verifyLiveRangeSegment(LR, I, Reg, LaneMask);
}
void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
verifyLiveRange(LI, LI.reg);
+ unsigned Reg = LI.reg;
+ if (TargetRegisterInfo::isVirtualRegister(Reg)) {
+ unsigned Mask = 0;
+ unsigned MaxMask = MRI->getMaxLaneMaskForVReg(Reg);
+ for (const LiveInterval::SubRange &SR : LI.subranges()) {
+ if ((Mask & SR.LaneMask) != 0)
+ report("Lane masks of sub ranges overlap in live interval", MF, LI);
+ if ((SR.LaneMask & ~MaxMask) != 0)
+ report("Subrange lanemask is invalid", MF, LI);
+ Mask |= SR.LaneMask;
+ verifyLiveRange(SR, LI.reg, SR.LaneMask);
+ if (!LI.covers(SR))
+ report("A Subrange is not covered by the main range", MF, LI);
+ }
+ } else if (LI.hasSubRanges()) {
+ report("subregister liveness only allowed for virtual registers", MF, LI);
+ }
+
// Check the LI only has one connected component.
if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
ConnectedVNInfoEqClasses ConEQ(*LiveInts);
if (NumComp > 1) {
report("Multiple connected components in live interval", MF, LI);
for (unsigned comp = 0; comp != NumComp; ++comp) {
- *OS << comp << ": valnos";
+ errs() << comp << ": valnos";
for (LiveInterval::const_vni_iterator I = LI.vni_begin(),
E = LI.vni_end(); I!=E; ++I)
if (comp == ConEQ.getEqClass(*I))
- *OS << ' ' << (*I)->id;
- *OS << '\n';
+ errs() << ' ' << (*I)->id;
+ errs() << '\n';
}
}
}
BBState.ExitValue;
if (BBState.ExitIsSetup && AbsSPAdj != Size) {
report("FrameDestroy <n> is after FrameSetup <m>", &I);
- *OS << "FrameDestroy <" << Size << "> is after FrameSetup <"
+ errs() << "FrameDestroy <" << Size << "> is after FrameSetup <"
<< AbsSPAdj << ">.\n";
}
BBState.ExitValue += Size;
(SPState[(*I)->getNumber()].ExitValue != BBState.EntryValue ||
SPState[(*I)->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
report("The exit stack state of a predecessor is inconsistent.", MBB);
- *OS << "Predecessor BB#" << (*I)->getNumber() << " has exit state ("
+ errs() << "Predecessor BB#" << (*I)->getNumber() << " has exit state ("
<< SPState[(*I)->getNumber()].ExitValue << ", "
<< SPState[(*I)->getNumber()].ExitIsSetup
<< "), while BB#" << MBB->getNumber() << " has entry state ("
(SPState[(*I)->getNumber()].EntryValue != BBState.ExitValue ||
SPState[(*I)->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
report("The entry stack state of a successor is inconsistent.", MBB);
- *OS << "Successor BB#" << (*I)->getNumber() << " has entry state ("
+ errs() << "Successor BB#" << (*I)->getNumber() << " has entry state ("
<< SPState[(*I)->getNumber()].EntryValue << ", "
<< SPState[(*I)->getNumber()].EntryIsSetup
<< "), while BB#" << MBB->getNumber() << " has exit state ("
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