class MCRegisterInfo;
class MCSubtargetInfo;
class Target;
+class Triple;
class StringRef;
class raw_pwrite_stream;
class raw_ostream;
extern Target TheSparcTarget;
extern Target TheSparcV9Target;
+extern Target TheSparcelTarget;
MCCodeEmitter *createSparcMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx);
-MCAsmBackend *createSparcAsmBackend(const Target &T,
- const MCRegisterInfo &MRI,
- StringRef TT,
- StringRef CPU);
+MCAsmBackend *createSparcAsmBackend(const Target &T, const MCRegisterInfo &MRI,
+ const Triple &TT, StringRef CPU);
MCObjectWriter *createSparcELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit,
- uint8_t OSABI);
+ bool IsLIttleEndian, uint8_t OSABI);
} // End llvm namespace
// Defines symbolic names for Sparc registers. This defines a mapping from