Update aosp/master llvm for rebase to r233350

[android-x86/external-llvm.git] / test / CodeGen / X86 / sha.ll

diff --git a/test/CodeGen/X86/sha.ll b/test/CodeGen/X86/sha.ll
index bf81e99..fe42637 100644 (file)
--- a/test/CodeGen/X86/sha.ll
+++ b/test/CodeGen/X86/sha.ll
@@ -13,7 +13,7 @@ entry:
 
 define <4 x i32> @test_sha1rnds4rm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable {
 entry:
-  %0 = load <4 x i32>* %b
+  %0 = load <4 x i32>, <4 x i32>* %b
   %1 = tail call <4 x i32> @llvm.x86.sha1rnds4(<4 x i32> %a, <4 x i32> %0, i8 3)
   ret <4 x i32> %1
   ; CHECK: test_sha1rnds4rm
@@ -32,7 +32,7 @@ entry:
 
 define <4 x i32> @test_sha1nexterm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable {
 entry:
-  %0 = load <4 x i32>* %b
+  %0 = load <4 x i32>, <4 x i32>* %b
   %1 = tail call <4 x i32> @llvm.x86.sha1nexte(<4 x i32> %a, <4 x i32> %0)
   ret <4 x i32> %1
   ; CHECK: test_sha1nexterm
@@ -51,7 +51,7 @@ entry:
 
 define <4 x i32> @test_sha1msg1rm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable {
 entry:
-  %0 = load <4 x i32>* %b
+  %0 = load <4 x i32>, <4 x i32>* %b
   %1 = tail call <4 x i32> @llvm.x86.sha1msg1(<4 x i32> %a, <4 x i32> %0)
   ret <4 x i32> %1
   ; CHECK: test_sha1msg1rm
@@ -70,7 +70,7 @@ entry:
 
 define <4 x i32> @test_sha1msg2rm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable {
 entry:
-  %0 = load <4 x i32>* %b
+  %0 = load <4 x i32>, <4 x i32>* %b
   %1 = tail call <4 x i32> @llvm.x86.sha1msg2(<4 x i32> %a, <4 x i32> %0)
   ret <4 x i32> %1
   ; CHECK: test_sha1msg2rm
@@ -91,7 +91,7 @@ entry:
 
 define <4 x i32> @test_sha256rnds2rm(<4 x i32> %a, <4 x i32>* %b, <4 x i32> %c) nounwind uwtable {
 entry:
-  %0 = load <4 x i32>* %b
+  %0 = load <4 x i32>, <4 x i32>* %b
   %1 = tail call <4 x i32> @llvm.x86.sha256rnds2(<4 x i32> %a, <4 x i32> %0, <4 x i32> %c)
   ret <4 x i32> %1
   ; CHECK: test_sha256rnds2rm
@@ -112,7 +112,7 @@ entry:
 
 define <4 x i32> @test_sha256msg1rm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable {
 entry:
-  %0 = load <4 x i32>* %b
+  %0 = load <4 x i32>, <4 x i32>* %b
   %1 = tail call <4 x i32> @llvm.x86.sha256msg1(<4 x i32> %a, <4 x i32> %0)
   ret <4 x i32> %1
   ; CHECK: test_sha256msg1rm
@@ -131,7 +131,7 @@ entry:
 
 define <4 x i32> @test_sha256msg2rm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable {
 entry:
-  %0 = load <4 x i32>* %b
+  %0 = load <4 x i32>, <4 x i32>* %b
   %1 = tail call <4 x i32> @llvm.x86.sha256msg2(<4 x i32> %a, <4 x i32> %0)
   ret <4 x i32> %1
   ; CHECK: test_sha256msg2rm