[DAGCombine] Catch the case where extract_vector_elt can cause an any_ext while proce...

[DAGCombine] Catch the case where extract_vector_elt can cause an any_ext while processing AND SDNodes

Summary:
extract_vector_elt can cause an implicit any_ext if the types don't
match. When processing the following pattern:

  (and (extract_vector_elt (load ([non_ext|any_ext|zero_ext] V))), c)

DAGCombine was ignoring the possible extend, and sometimes removing
the AND even though it was required to maintain some of the bits
in the result to 0, resulting in a miscompile.

This change fixes the issue by limiting the transformation only to
cases where the extract_vector_elt doesn't perform the implicit
extend.

Reviewers: t.p.northover, jmolloy

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D18247

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263935 91177308-0d34-0410-b5e6-96231b3b80d8