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[tablegen] Improve performance on *GenRegisterInfo.inc by replacing SparseVector...
authorDaniel Sanders <daniel_l_sanders@apple.com>
Fri, 8 Jun 2018 23:12:29 +0000 (23:12 +0000)
committerDaniel Sanders <daniel_l_sanders@apple.com>
Fri, 8 Jun 2018 23:12:29 +0000 (23:12 +0000)
commitf5137255b64252669f1917eda9d5b7ee648f6be4
tree8dfac4acdf6b2d2c76652de84e4e3223ca0a8411tree | snapshot
parent3f7dfd74cf818b62e2f08835cd35cd23c314ccb2commit | diff
[tablegen] Improve performance on *GenRegisterInfo.inc by replacing SparseVector with BitVector. NFC

Summary: Generating X86GenRegisterInfo.inc and AArch64GenRegisterInfo.inc is 8-9% faster on my build.

Reviewers: bogner, javed.absar

Reviewed By: bogner

Subscribers: llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D47907

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334337 91177308-0d34-0410-b5e6-96231b3b80d8
utils/TableGen/CodeGenRegisters.cpp diff | blob | history
external/llvm
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