Merge freedesktop/master into otc-private/master

[android-x86/external-mesa.git] / src / mesa / drivers / dri / intel / intel_chipset.h

diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h
index ee735bb..1e98cf4 100644 (file)
--- a/src/mesa/drivers/dri/intel/intel_chipset.h
+++ b/src/mesa/drivers/dri/intel/intel_chipset.h
@@ -102,6 +102,12 @@
 #define PCI_CHIP_HASWELL_S_GT1          0x040A /* Server */
 #define PCI_CHIP_HASWELL_S_GT2          0x041A
 #define PCI_CHIP_HASWELL_S_GT3          0x042A
+#define PCI_CHIP_HASWELL_B_GT1          0x040B /* Reserved */
+#define PCI_CHIP_HASWELL_B_GT2          0x041B
+#define PCI_CHIP_HASWELL_B_GT3          0x042B
+#define PCI_CHIP_HASWELL_E_GT1          0x040E /* Reserved */
+#define PCI_CHIP_HASWELL_E_GT2          0x041E
+#define PCI_CHIP_HASWELL_E_GT3          0x042E
 #define PCI_CHIP_HASWELL_SDV_GT1        0x0C02 /* Desktop */
 #define PCI_CHIP_HASWELL_SDV_GT2        0x0C12
 #define PCI_CHIP_HASWELL_SDV_GT3        0x0C22
@@ -111,6 +117,12 @@
 #define PCI_CHIP_HASWELL_SDV_S_GT1      0x0C0A /* Server */
 #define PCI_CHIP_HASWELL_SDV_S_GT2      0x0C1A
 #define PCI_CHIP_HASWELL_SDV_S_GT3      0x0C2A
+#define PCI_CHIP_HASWELL_SDV_B_GT1      0x0C0B /* Reserved */
+#define PCI_CHIP_HASWELL_SDV_B_GT2      0x0C1B
+#define PCI_CHIP_HASWELL_SDV_B_GT3      0x0C2B
+#define PCI_CHIP_HASWELL_SDV_E_GT1      0x0C0E /* Reserved */
+#define PCI_CHIP_HASWELL_SDV_E_GT2      0x0C1E
+#define PCI_CHIP_HASWELL_SDV_E_GT3      0x0C2E
 #define PCI_CHIP_HASWELL_ULT_GT1        0x0A02 /* Desktop */
 #define PCI_CHIP_HASWELL_ULT_GT2        0x0A12
 #define PCI_CHIP_HASWELL_ULT_GT3        0x0A22
@@ -120,6 +132,12 @@
 #define PCI_CHIP_HASWELL_ULT_S_GT1      0x0A0A /* Server */
 #define PCI_CHIP_HASWELL_ULT_S_GT2      0x0A1A
 #define PCI_CHIP_HASWELL_ULT_S_GT3      0x0A2A
+#define PCI_CHIP_HASWELL_ULT_B_GT1      0x0A0B /* Reserved */
+#define PCI_CHIP_HASWELL_ULT_B_GT2      0x0A1B
+#define PCI_CHIP_HASWELL_ULT_B_GT3      0x0A2B
+#define PCI_CHIP_HASWELL_ULT_E_GT1      0x0A0E /* Reserved */
+#define PCI_CHIP_HASWELL_ULT_E_GT2      0x0A1E
+#define PCI_CHIP_HASWELL_ULT_E_GT3      0x0A2E
 #define PCI_CHIP_HASWELL_CRW_GT1        0x0D02 /* Desktop */
 #define PCI_CHIP_HASWELL_CRW_GT2        0x0D12
 #define PCI_CHIP_HASWELL_CRW_GT3        0x0D22
@@ -129,6 +147,12 @@
 #define PCI_CHIP_HASWELL_CRW_S_GT1      0x0D0A /* Server */
 #define PCI_CHIP_HASWELL_CRW_S_GT2      0x0D1A
 #define PCI_CHIP_HASWELL_CRW_S_GT3      0x0D2A
+#define PCI_CHIP_HASWELL_CRW_B_GT1      0x0D0B /* Reserved */
+#define PCI_CHIP_HASWELL_CRW_B_GT2      0x0D1B
+#define PCI_CHIP_HASWELL_CRW_B_GT3      0x0D2B
+#define PCI_CHIP_HASWELL_CRW_E_GT1      0x0D0E /* Reserved */
+#define PCI_CHIP_HASWELL_CRW_E_GT2      0x0D1E
+#define PCI_CHIP_HASWELL_CRW_E_GT3      0x0D2E
 
 #define IS_MOBILE(devid)       (devid == PCI_CHIP_I855_GM || \
                                 devid == PCI_CHIP_I915_GM || \
@@ -209,39 +233,63 @@
 #define IS_HSW_GT1(devid)      (devid == PCI_CHIP_HASWELL_GT1 || \
                                 devid == PCI_CHIP_HASWELL_M_GT1 || \
                                 devid == PCI_CHIP_HASWELL_S_GT1 || \
+                                devid == PCI_CHIP_HASWELL_B_GT1 || \
+                                devid == PCI_CHIP_HASWELL_E_GT1 || \
                                 devid == PCI_CHIP_HASWELL_SDV_GT1 || \
                                 devid == PCI_CHIP_HASWELL_SDV_M_GT1 || \
                                 devid == PCI_CHIP_HASWELL_SDV_S_GT1 || \
+                                devid == PCI_CHIP_HASWELL_SDV_B_GT1 || \
+                                devid == PCI_CHIP_HASWELL_SDV_E_GT1 || \
                                 devid == PCI_CHIP_HASWELL_ULT_GT1 || \
                                 devid == PCI_CHIP_HASWELL_ULT_M_GT1 || \
                                 devid == PCI_CHIP_HASWELL_ULT_S_GT1 || \
+                                devid == PCI_CHIP_HASWELL_ULT_B_GT1 || \
+                                devid == PCI_CHIP_HASWELL_ULT_E_GT1 || \
                                 devid == PCI_CHIP_HASWELL_CRW_GT1 || \
                                 devid == PCI_CHIP_HASWELL_CRW_M_GT1 || \
-                                devid == PCI_CHIP_HASWELL_CRW_S_GT1)
+                                devid == PCI_CHIP_HASWELL_CRW_S_GT1 || \
+                                devid == PCI_CHIP_HASWELL_CRW_B_GT1 || \
+                                devid == PCI_CHIP_HASWELL_CRW_E_GT1)
 #define IS_HSW_GT2(devid)      (devid == PCI_CHIP_HASWELL_GT2 || \
                                 devid == PCI_CHIP_HASWELL_M_GT2 || \
                                 devid == PCI_CHIP_HASWELL_S_GT2 || \
+                                devid == PCI_CHIP_HASWELL_B_GT2 || \
+                                devid == PCI_CHIP_HASWELL_E_GT2 || \
                                 devid == PCI_CHIP_HASWELL_SDV_GT2 || \
                                 devid == PCI_CHIP_HASWELL_SDV_M_GT2 || \
                                 devid == PCI_CHIP_HASWELL_SDV_S_GT2 || \
+                                devid == PCI_CHIP_HASWELL_SDV_B_GT2 || \
+                                devid == PCI_CHIP_HASWELL_SDV_E_GT2 || \
                                 devid == PCI_CHIP_HASWELL_ULT_GT2 || \
                                 devid == PCI_CHIP_HASWELL_ULT_M_GT2 || \
                                 devid == PCI_CHIP_HASWELL_ULT_S_GT2 || \
+                                devid == PCI_CHIP_HASWELL_ULT_B_GT2 || \
+                                devid == PCI_CHIP_HASWELL_ULT_E_GT2 || \
                                 devid == PCI_CHIP_HASWELL_CRW_GT2 || \
                                 devid == PCI_CHIP_HASWELL_CRW_M_GT2 || \
-                                devid == PCI_CHIP_HASWELL_CRW_S_GT2)
+                                devid == PCI_CHIP_HASWELL_CRW_S_GT2 || \
+                                devid == PCI_CHIP_HASWELL_CRW_B_GT2 || \
+                                devid == PCI_CHIP_HASWELL_CRW_E_GT2)
 #define IS_HSW_GT3(devid)      (devid == PCI_CHIP_HASWELL_GT3 || \
                                 devid == PCI_CHIP_HASWELL_M_GT3 || \
                                 devid == PCI_CHIP_HASWELL_S_GT3 || \
+                                devid == PCI_CHIP_HASWELL_B_GT3 || \
+                                devid == PCI_CHIP_HASWELL_E_GT3 || \
                                 devid == PCI_CHIP_HASWELL_SDV_GT3 || \
                                 devid == PCI_CHIP_HASWELL_SDV_M_GT3 || \
                                 devid == PCI_CHIP_HASWELL_SDV_S_GT3 || \
+                                devid == PCI_CHIP_HASWELL_SDV_B_GT3 || \
+                                devid == PCI_CHIP_HASWELL_SDV_E_GT3 || \
                                 devid == PCI_CHIP_HASWELL_ULT_GT3 || \
                                 devid == PCI_CHIP_HASWELL_ULT_M_GT3 || \
                                 devid == PCI_CHIP_HASWELL_ULT_S_GT3 || \
+                                devid == PCI_CHIP_HASWELL_ULT_B_GT3 || \
+                                devid == PCI_CHIP_HASWELL_ULT_E_GT3 || \
                                 devid == PCI_CHIP_HASWELL_CRW_GT3 || \
                                 devid == PCI_CHIP_HASWELL_CRW_M_GT3 || \
-                                devid == PCI_CHIP_HASWELL_CRW_S_GT3)
+                                devid == PCI_CHIP_HASWELL_CRW_S_GT3 || \
+                                devid == PCI_CHIP_HASWELL_CRW_B_GT3 || \
+                                devid == PCI_CHIP_HASWELL_CRW_E_GT3)
 
 #define IS_HASWELL(devid)       (IS_HSW_GT1(devid) || \
                                 IS_HSW_GT2(devid) || \