i965/skl: Use 1 register for uniform pull constant payload

i965/skl: Use 1 register for uniform pull constant payload

When under dispatch_width=16 the previous code would allocate 2 registers for
the payload when only one is needed. This manifested itself through bugs on SKL
which needs to mess with this instruction.

Ken thought this might impact shader-db, but apparently it doesn't

Backported to 10.5.8 from (upstream uses alloc.allocate()):
commit 6e62a52865787362ae1deb9dee80140d3a66c519
Author: Ben Widawsky <benjamin.widawsky@intel.com>
Date:   Thu Feb 19 15:49:34 2015 -0800

    i965/skl: Use 1 register for uniform pull constant payload

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89118
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88999
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Timo Aaltonen <timo.aaltonen@canonical.com>
Cc: "10.5" <mesa-stable@lists.freedesktop.org>