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(parent: 47b390f) | patch
genxml/hsw: Add L3 cache control registers
authorJordan Justen <jordan.l.justen@intel.com>
Sat, 2 Apr 2016 08:25:05 +0000 (01:25 -0700)
committerJordan Justen <jordan.l.justen@intel.com>
Tue, 17 May 2016 20:04:03 +0000 (13:04 -0700)
commitff417388719828b3b5f0c9e3c0b076e9cff99ff7
treea6966c5f7d87f9dd540dc366eb462f77dc1474d1tree | snapshot
parent47b390fe45e5e6f982c60b58985892438959cd8ecommit | diff
genxml/hsw: Add L3 cache control registers

These were added to the i965 driver in
5912da45a69923afa1b7f2eb5bb371d848813c41.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
src/intel/genxml/gen75.xml diff | blob | history
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