amdgpu.c

   1 /*
   2  * Copyright 2016 The Chromium OS Authors. All rights reserved.
   3  * Use of this source code is governed by a BSD-style license that can be
   4  * found in the LICENSE file.
   5  */
   6 #ifdef DRV_AMDGPU
   7 #include <amdgpu.h>
   8 #include <amdgpu_drm.h>
   9 #include <errno.h>
  10 #include <stdio.h>
  11 #include <stdlib.h>
  12 #include <string.h>
  13 #include <sys/mman.h>
  14 #include <xf86drm.h>
  15
  16 #include "addrinterface.h"
  17 #include "drv_priv.h"
  18 #include "helpers.h"
  19 #include "util.h"
  20
  21 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
  22 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
  23 #endif
  24
  25 // clang-format off
  26 #define mmCC_RB_BACKEND_DISABLE         0x263d
  27 #define mmGB_TILE_MODE0                 0x2644
  28 #define mmGB_MACROTILE_MODE0            0x2664
  29 #define mmGB_ADDR_CONFIG                0x263e
  30 #define mmMC_ARB_RAMCFG                 0x9d8
  31
  32 enum {
  33         FAMILY_UNKNOWN,
  34         FAMILY_SI,
  35         FAMILY_CI,
  36         FAMILY_KV,
  37         FAMILY_VI,
  38         FAMILY_CZ,
  39         FAMILY_PI,
  40         FAMILY_LAST,
  41 };
  42 // clang-format on
  43
  44 const static uint32_t render_target_formats[] = { DRM_FORMAT_ARGB8888, DRM_FORMAT_RGB565,
  45                                                   DRM_FORMAT_XBGR8888, DRM_FORMAT_XRGB8888 };
  46
  47 const static uint32_t texture_source_formats[] = { DRM_FORMAT_GR88, DRM_FORMAT_R8, DRM_FORMAT_NV21,
  48                                                    DRM_FORMAT_NV12 };
  49
  50 static int amdgpu_set_metadata(int fd, uint32_t handle, struct amdgpu_bo_metadata *info)
  51 {
  52         struct drm_amdgpu_gem_metadata args = { 0 };
  53
  54         if (!info)
  55                 return -EINVAL;
  56
  57         args.handle = handle;
  58         args.op = AMDGPU_GEM_METADATA_OP_SET_METADATA;
  59         args.data.flags = info->flags;
  60         args.data.tiling_info = info->tiling_info;
  61
  62         if (info->size_metadata > sizeof(args.data.data))
  63                 return -EINVAL;
  64
  65         if (info->size_metadata) {
  66                 args.data.data_size_bytes = info->size_metadata;
  67                 memcpy(args.data.data, info->umd_metadata, info->size_metadata);
  68         }
  69
  70         return drmCommandWriteRead(fd, DRM_AMDGPU_GEM_METADATA, &args, sizeof(args));
  71 }
  72
  73 static int amdgpu_read_mm_regs(int fd, unsigned dword_offset, unsigned count, uint32_t instance,
  74                                uint32_t flags, uint32_t *values)
  75 {
  76         struct drm_amdgpu_info request;
  77
  78         memset(&request, 0, sizeof(request));
  79         request.return_pointer = (uintptr_t)values;
  80         request.return_size = count * sizeof(uint32_t);
  81         request.query = AMDGPU_INFO_READ_MMR_REG;
  82         request.read_mmr_reg.dword_offset = dword_offset;
  83         request.read_mmr_reg.count = count;
  84         request.read_mmr_reg.instance = instance;
  85         request.read_mmr_reg.flags = flags;
  86
  87         return drmCommandWrite(fd, DRM_AMDGPU_INFO, &request, sizeof(struct drm_amdgpu_info));
  88 }
  89
  90 static int amdgpu_query_gpu(int fd, struct amdgpu_gpu_info *gpu_info)
  91 {
  92         int ret;
  93         uint32_t instance;
  94
  95         if (!gpu_info)
  96                 return -EINVAL;
  97
  98         instance = AMDGPU_INFO_MMR_SH_INDEX_MASK << AMDGPU_INFO_MMR_SH_INDEX_SHIFT;
  99
 100         ret = amdgpu_read_mm_regs(fd, mmCC_RB_BACKEND_DISABLE, 1, instance, 0,
 101                                   &gpu_info->backend_disable[0]);
 102         if (ret)
 103                 return ret;
 104         /* extract bitfield CC_RB_BACKEND_DISABLE.BACKEND_DISABLE */
 105         gpu_info->backend_disable[0] = (gpu_info->backend_disable[0] >> 16) & 0xff;
 106
 107         ret = amdgpu_read_mm_regs(fd, mmGB_TILE_MODE0, 32, 0xffffffff, 0, gpu_info->gb_tile_mode);
 108         if (ret)
 109                 return ret;
 110
 111         ret = amdgpu_read_mm_regs(fd, mmGB_MACROTILE_MODE0, 16, 0xffffffff, 0,
 112                                   gpu_info->gb_macro_tile_mode);
 113         if (ret)
 114                 return ret;
 115
 116         ret = amdgpu_read_mm_regs(fd, mmGB_ADDR_CONFIG, 1, 0xffffffff, 0, &gpu_info->gb_addr_cfg);
 117         if (ret)
 118                 return ret;
 119
 120         ret = amdgpu_read_mm_regs(fd, mmMC_ARB_RAMCFG, 1, 0xffffffff, 0, &gpu_info->mc_arb_ramcfg);
 121         if (ret)
 122                 return ret;
 123
 124         return 0;
 125 }
 126
 127 static void *ADDR_API alloc_sys_mem(const ADDR_ALLOCSYSMEM_INPUT *in)
 128 {
 129         return malloc(in->sizeInBytes);
 130 }
 131
 132 static ADDR_E_RETURNCODE ADDR_API free_sys_mem(const ADDR_FREESYSMEM_INPUT *in)
 133 {
 134         free(in->pVirtAddr);
 135         return ADDR_OK;
 136 }
 137
 138 static int amdgpu_addrlib_compute(void *addrlib, uint32_t width, uint32_t height, uint32_t format,
 139                                   uint64_t use_flags, uint32_t *tiling_flags,
 140                                   ADDR_COMPUTE_SURFACE_INFO_OUTPUT *addr_out)
 141 {
 142         ADDR_COMPUTE_SURFACE_INFO_INPUT addr_surf_info_in = { 0 };
 143         ADDR_TILEINFO addr_tile_info = { 0 };
 144         ADDR_TILEINFO addr_tile_info_out = { 0 };
 145         uint32_t bits_per_pixel;
 146
 147         addr_surf_info_in.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
 148
 149         /* Set the requested tiling mode. */
 150         addr_surf_info_in.tileMode = ADDR_TM_2D_TILED_THIN1;
 151         if (use_flags &
 152             (BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN))
 153                 addr_surf_info_in.tileMode = ADDR_TM_LINEAR_ALIGNED;
 154         else if (width <= 16 || height <= 16)
 155                 addr_surf_info_in.tileMode = ADDR_TM_1D_TILED_THIN1;
 156
 157         bits_per_pixel = drv_stride_from_format(format, 1, 0) * 8;
 158         /* Bits per pixel should be calculated from format*/
 159         addr_surf_info_in.bpp = bits_per_pixel;
 160         addr_surf_info_in.numSamples = 1;
 161         addr_surf_info_in.width = width;
 162         addr_surf_info_in.height = height;
 163         addr_surf_info_in.numSlices = 1;
 164         addr_surf_info_in.pTileInfo = &addr_tile_info;
 165         addr_surf_info_in.tileIndex = -1;
 166
 167         /* This disables incorrect calculations (hacks) in addrlib. */
 168         addr_surf_info_in.flags.noStencil = 1;
 169
 170         /* Set the micro tile type. */
 171         if (use_flags & BO_USE_SCANOUT)
 172                 addr_surf_info_in.tileType = ADDR_DISPLAYABLE;
 173         else
 174                 addr_surf_info_in.tileType = ADDR_NON_DISPLAYABLE;
 175
 176         addr_out->size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
 177         addr_out->pTileInfo = &addr_tile_info_out;
 178
 179         if (AddrComputeSurfaceInfo(addrlib, &addr_surf_info_in, addr_out) != ADDR_OK)
 180                 return -EINVAL;
 181
 182         ADDR_CONVERT_TILEINFOTOHW_INPUT s_in = { 0 };
 183         ADDR_CONVERT_TILEINFOTOHW_OUTPUT s_out = { 0 };
 184         ADDR_TILEINFO s_tile_hw_info_out = { 0 };
 185
 186         s_in.size = sizeof(ADDR_CONVERT_TILEINFOTOHW_INPUT);
 187         /* Convert from real value to HW value */
 188         s_in.reverse = 0;
 189         s_in.pTileInfo = &addr_tile_info_out;
 190         s_in.tileIndex = -1;
 191
 192         s_out.size = sizeof(ADDR_CONVERT_TILEINFOTOHW_OUTPUT);
 193         s_out.pTileInfo = &s_tile_hw_info_out;
 194
 195         if (AddrConvertTileInfoToHW(addrlib, &s_in, &s_out) != ADDR_OK)
 196                 return -EINVAL;
 197
 198         if (addr_out->tileMode >= ADDR_TM_2D_TILED_THIN1)
 199                 /* 2D_TILED_THIN1 */
 200                 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4);
 201         else if (addr_out->tileMode >= ADDR_TM_1D_TILED_THIN1)
 202                 /* 1D_TILED_THIN1 */
 203                 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 2);
 204         else
 205                 /* LINEAR_ALIGNED */
 206                 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 1);
 207
 208         *tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, drv_log_base2(addr_tile_info_out.bankWidth));
 209         *tiling_flags |=
 210             AMDGPU_TILING_SET(BANK_HEIGHT, drv_log_base2(addr_tile_info_out.bankHeight));
 211         *tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT, s_tile_hw_info_out.tileSplitBytes);
 212         *tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT,
 213                                            drv_log_base2(addr_tile_info_out.macroAspectRatio));
 214         *tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, s_tile_hw_info_out.pipeConfig);
 215         *tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, s_tile_hw_info_out.banks);
 216
 217         return 0;
 218 }
 219
 220 static void *amdgpu_addrlib_init(int fd)
 221 {
 222         int ret;
 223         ADDR_CREATE_INPUT addr_create_input = { 0 };
 224         ADDR_CREATE_OUTPUT addr_create_output = { 0 };
 225         ADDR_REGISTER_VALUE reg_value = { 0 };
 226         ADDR_CREATE_FLAGS create_flags = { { 0 } };
 227         ADDR_E_RETURNCODE addr_ret;
 228
 229         addr_create_input.size = sizeof(ADDR_CREATE_INPUT);
 230         addr_create_output.size = sizeof(ADDR_CREATE_OUTPUT);
 231
 232         struct amdgpu_gpu_info gpu_info = { 0 };
 233
 234         ret = amdgpu_query_gpu(fd, &gpu_info);
 235
 236         if (ret) {
 237                 fprintf(stderr, "[%s]failed with error =%d\n", __func__, ret);
 238                 return NULL;
 239         }
 240
 241         reg_value.noOfBanks = gpu_info.mc_arb_ramcfg & 0x3;
 242         reg_value.gbAddrConfig = gpu_info.gb_addr_cfg;
 243         reg_value.noOfRanks = (gpu_info.mc_arb_ramcfg & 0x4) >> 2;
 244
 245         reg_value.backendDisables = gpu_info.backend_disable[0];
 246         reg_value.pTileConfig = gpu_info.gb_tile_mode;
 247         reg_value.noOfEntries = sizeof(gpu_info.gb_tile_mode) / sizeof(gpu_info.gb_tile_mode[0]);
 248         reg_value.pMacroTileConfig = gpu_info.gb_macro_tile_mode;
 249         reg_value.noOfMacroEntries =
 250             sizeof(gpu_info.gb_macro_tile_mode) / sizeof(gpu_info.gb_macro_tile_mode[0]);
 251         create_flags.value = 0;
 252         create_flags.useTileIndex = 1;
 253
 254         addr_create_input.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
 255
 256         addr_create_input.chipFamily = FAMILY_CZ;
 257         addr_create_input.createFlags = create_flags;
 258         addr_create_input.callbacks.allocSysMem = alloc_sys_mem;
 259         addr_create_input.callbacks.freeSysMem = free_sys_mem;
 260         addr_create_input.callbacks.debugPrint = 0;
 261         addr_create_input.regValue = reg_value;
 262
 263         addr_ret = AddrCreate(&addr_create_input, &addr_create_output);
 264
 265         if (addr_ret != ADDR_OK) {
 266                 fprintf(stderr, "[%s]failed error =%d\n", __func__, addr_ret);
 267                 return NULL;
 268         }
 269
 270         return addr_create_output.hLib;
 271 }
 272
 273 static int amdgpu_init(struct driver *drv)
 274 {
 275         int ret;
 276         void *addrlib;
 277         struct format_metadata metadata;
 278         uint64_t use_flags = BO_USE_RENDER_MASK;
 279
 280         addrlib = amdgpu_addrlib_init(drv_get_fd(drv));
 281         if (!addrlib)
 282                 return -1;
 283
 284         drv->priv = addrlib;
 285
 286         ret = drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
 287                                    &LINEAR_METADATA, BO_USE_TEXTURE_MASK);
 288         if (ret)
 289                 return ret;
 290
 291         drv_modify_combination(drv, DRM_FORMAT_NV21, &LINEAR_METADATA, BO_USE_SCANOUT);
 292         drv_modify_combination(drv, DRM_FORMAT_NV12, &LINEAR_METADATA, BO_USE_SCANOUT);
 293
 294         metadata.tiling = ADDR_DISPLAYABLE << 16 | ADDR_TM_LINEAR_ALIGNED;
 295         metadata.priority = 2;
 296         metadata.modifier = DRM_FORMAT_MOD_LINEAR;
 297
 298         ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
 299                                    &metadata, use_flags);
 300         if (ret)
 301                 return ret;
 302
 303         drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
 304         drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
 305         drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT);
 306
 307         metadata.tiling = ADDR_NON_DISPLAYABLE << 16 | ADDR_TM_LINEAR_ALIGNED;
 308         metadata.priority = 3;
 309         metadata.modifier = DRM_FORMAT_MOD_LINEAR;
 310
 311         ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
 312                                    &metadata, use_flags);
 313         if (ret)
 314                 return ret;
 315
 316         use_flags &= ~BO_USE_SW_WRITE_OFTEN;
 317         use_flags &= ~BO_USE_SW_READ_OFTEN;
 318         use_flags &= ~BO_USE_LINEAR;
 319
 320         metadata.tiling = ADDR_DISPLAYABLE << 16 | ADDR_TM_2D_TILED_THIN1;
 321         metadata.priority = 4;
 322
 323         ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
 324                                    &metadata, use_flags);
 325         if (ret)
 326                 return ret;
 327
 328         drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_SCANOUT);
 329         drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_SCANOUT);
 330         drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT);
 331
 332         metadata.tiling = ADDR_NON_DISPLAYABLE << 16 | ADDR_TM_2D_TILED_THIN1;
 333         metadata.priority = 5;
 334
 335         ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
 336                                    &metadata, use_flags);
 337         if (ret)
 338                 return ret;
 339
 340         return ret;
 341 }
 342
 343 static void amdgpu_close(struct driver *drv)
 344 {
 345         AddrDestroy(drv->priv);
 346         drv->priv = NULL;
 347 }
 348
 349 static int amdgpu_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
 350                             uint64_t use_flags)
 351 {
 352         void *addrlib = bo->drv->priv;
 353         union drm_amdgpu_gem_create gem_create;
 354         struct amdgpu_bo_metadata metadata = { 0 };
 355         ADDR_COMPUTE_SURFACE_INFO_OUTPUT addr_out = { 0 };
 356         uint32_t tiling_flags = 0;
 357         size_t plane;
 358         int ret;
 359
 360         if (format == DRM_FORMAT_NV12 || format == DRM_FORMAT_NV21) {
 361                 drv_bo_from_format(bo, ALIGN(width, 64), height, format);
 362         } else {
 363                 if (amdgpu_addrlib_compute(addrlib, width, height, format, use_flags, &tiling_flags,
 364                                            &addr_out) < 0)
 365                         return -EINVAL;
 366
 367                 bo->tiling = tiling_flags;
 368                 /* RGB has 1 plane only */
 369                 bo->offsets[0] = 0;
 370                 bo->total_size = bo->sizes[0] = addr_out.surfSize;
 371                 bo->strides[0] = addr_out.pixelPitch * DIV_ROUND_UP(addr_out.pixelBits, 8);
 372         }
 373
 374         memset(&gem_create, 0, sizeof(gem_create));
 375
 376         gem_create.in.bo_size = bo->total_size;
 377         gem_create.in.alignment = addr_out.baseAlign;
 378         /* Set the placement. */
 379         gem_create.in.domains = AMDGPU_GEM_DOMAIN_VRAM;
 380         gem_create.in.domain_flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 381         /* Allocate the buffer with the preferred heap. */
 382         ret = drmCommandWriteRead(drv_get_fd(bo->drv), DRM_AMDGPU_GEM_CREATE, &gem_create,
 383                                   sizeof(gem_create));
 384
 385         if (ret < 0)
 386                 return ret;
 387
 388         metadata.tiling_info = tiling_flags;
 389
 390         for (plane = 0; plane < bo->num_planes; plane++)
 391                 bo->handles[plane].u32 = gem_create.out.handle;
 392
 393         ret = amdgpu_set_metadata(drv_get_fd(bo->drv), bo->handles[0].u32, &metadata);
 394
 395         return ret;
 396 }
 397
 398 static void *amdgpu_bo_map(struct bo *bo, struct map_info *data, size_t plane, uint32_t map_flags)
 399 {
 400         int ret;
 401         union drm_amdgpu_gem_mmap gem_map;
 402
 403         memset(&gem_map, 0, sizeof(gem_map));
 404         gem_map.in.handle = bo->handles[plane].u32;
 405
 406         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_AMDGPU_GEM_MMAP, &gem_map);
 407         if (ret) {
 408                 fprintf(stderr, "drv: DRM_IOCTL_AMDGPU_GEM_MMAP failed\n");
 409                 return MAP_FAILED;
 410         }
 411
 412         data->length = bo->total_size;
 413
 414         return mmap(0, bo->total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
 415                     gem_map.out.addr_ptr);
 416 }
 417
 418 static uint32_t amdgpu_resolve_format(uint32_t format, uint64_t use_flags)
 419 {
 420         switch (format) {
 421         case DRM_FORMAT_FLEX_YCbCr_420_888:
 422                 return DRM_FORMAT_NV12;
 423         default:
 424                 return format;
 425         }
 426 }
 427
 428 struct backend backend_amdgpu = {
 429         .name = "amdgpu",
 430         .init = amdgpu_init,
 431         .close = amdgpu_close,
 432         .bo_create = amdgpu_bo_create,
 433         .bo_destroy = drv_gem_bo_destroy,
 434         .bo_import = drv_prime_bo_import,
 435         .bo_map = amdgpu_bo_map,
 436         .bo_unmap = drv_bo_munmap,
 437         .resolve_format = amdgpu_resolve_format,
 438 };
 439
 440 #endif