amdgpu.c

   1 /*
   2  * Copyright 2016 The Chromium OS Authors. All rights reserved.
   3  * Use of this source code is governed by a BSD-style license that can be
   4  * found in the LICENSE file.
   5  */
   6 #ifdef DRV_AMDGPU
   7 #include <amdgpu.h>
   8 #include <amdgpu_drm.h>
   9 #include <errno.h>
  10 #include <stdio.h>
  11 #include <stdlib.h>
  12 #include <string.h>
  13 #include <sys/mman.h>
  14 #include <xf86drm.h>
  15
  16 #include "dri.h"
  17 #include "drv_priv.h"
  18 #include "helpers.h"
  19 #include "util.h"
  20
  21 #ifdef __LP64__
  22 #define DRI_PATH "/vendor/lib64/dri/radeonsi_dri.so"
  23 #else
  24 #define DRI_PATH "/vendor/lib/dri/radeonsi_dri.so"
  25 #endif
  26
  27 #define TILE_TYPE_LINEAR 0
  28 /* DRI backend decides tiling in this case. */
  29 #define TILE_TYPE_DRI 1
  30
  31 struct amdgpu_priv {
  32         struct dri_driver dri;
  33         int drm_version;
  34 };
  35
  36 const static uint32_t render_target_formats[] = { DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB8888,
  37                                                   DRM_FORMAT_RGB565, DRM_FORMAT_XBGR8888,
  38                                                   DRM_FORMAT_XRGB8888 };
  39
  40 const static uint32_t texture_source_formats[] = { DRM_FORMAT_BGR888, DRM_FORMAT_GR88,
  41                                                    DRM_FORMAT_R8,     DRM_FORMAT_NV21,
  42                                                    DRM_FORMAT_NV12,   DRM_FORMAT_YVU420_ANDROID };
  43
  44 static int amdgpu_init(struct driver *drv)
  45 {
  46         struct amdgpu_priv *priv;
  47         drmVersionPtr drm_version;
  48         struct format_metadata metadata;
  49         uint64_t use_flags = BO_USE_RENDER_MASK;
  50
  51         priv = calloc(1, sizeof(struct amdgpu_priv));
  52         if (!priv)
  53                 return -ENOMEM;
  54
  55         drm_version = drmGetVersion(drv_get_fd(drv));
  56         if (!drm_version) {
  57                 free(priv);
  58                 return -ENODEV;
  59         }
  60
  61         priv->drm_version = drm_version->version_minor;
  62         drmFreeVersion(drm_version);
  63
  64         drv->priv = priv;
  65
  66         if (dri_init(drv, DRI_PATH, "radeonsi")) {
  67                 free(priv);
  68                 drv->priv = NULL;
  69                 return -ENODEV;
  70         }
  71
  72         metadata.tiling = TILE_TYPE_LINEAR;
  73         metadata.priority = 1;
  74         metadata.modifier = DRM_FORMAT_MOD_LINEAR;
  75
  76         drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
  77                              &metadata, use_flags);
  78
  79         drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
  80                              &metadata, BO_USE_TEXTURE_MASK);
  81
  82         /* Linear formats supported by display. */
  83         drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
  84         drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
  85         drv_modify_combination(drv, DRM_FORMAT_ABGR8888, &metadata, BO_USE_SCANOUT);
  86         drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT);
  87
  88         /* YUV formats for camera and display. */
  89         drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata,
  90                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_SCANOUT);
  91
  92         drv_modify_combination(drv, DRM_FORMAT_NV21, &metadata, BO_USE_SCANOUT);
  93
  94         /*
  95          * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots
  96          * from camera.
  97          */
  98         drv_modify_combination(drv, DRM_FORMAT_R8, &metadata,
  99                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
 100
 101         /*
 102          * The following formats will be allocated by the DRI backend and may be potentially tiled.
 103          * Since format modifier support hasn't been implemented fully yet, it's not
 104          * possible to enumerate the different types of buffers (like i915 can).
 105          */
 106         use_flags &= ~BO_USE_RENDERSCRIPT;
 107         use_flags &= ~BO_USE_SW_WRITE_OFTEN;
 108         use_flags &= ~BO_USE_SW_READ_OFTEN;
 109         use_flags &= ~BO_USE_LINEAR;
 110
 111         metadata.tiling = TILE_TYPE_DRI;
 112         metadata.priority = 2;
 113
 114         drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
 115                              &metadata, use_flags);
 116
 117         /* Potentially tiled formats supported by display. */
 118         drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
 119         drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
 120         drv_modify_combination(drv, DRM_FORMAT_ABGR8888, &metadata, BO_USE_SCANOUT);
 121         drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT);
 122         return 0;
 123 }
 124
 125 static void amdgpu_close(struct driver *drv)
 126 {
 127         dri_close(drv);
 128         free(drv->priv);
 129         drv->priv = NULL;
 130 }
 131
 132 static int amdgpu_create_bo(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
 133                             uint64_t use_flags)
 134 {
 135         int ret;
 136         uint32_t plane, stride;
 137         struct combination *combo;
 138         union drm_amdgpu_gem_create gem_create;
 139
 140         combo = drv_get_combination(bo->drv, format, use_flags);
 141         if (!combo)
 142                 return -EINVAL;
 143
 144         if (combo->metadata.tiling == TILE_TYPE_DRI) {
 145                 bool needs_alignment = false;
 146 #ifdef __ANDROID__
 147                 /*
 148                  * Currently, the gralloc API doesn't differentiate between allocation time and map
 149                  * time strides. A workaround for amdgpu DRI buffers is to always to align to 256 at
 150                  * allocation time.
 151                  *
 152                  * See b/115946221,b/117942643
 153                  */
 154                 if (use_flags & (BO_USE_SW_MASK))
 155                         needs_alignment = true;
 156 #endif
 157                 // See b/122049612
 158                 if (use_flags & (BO_USE_SCANOUT))
 159                         needs_alignment = true;
 160
 161                 if (needs_alignment) {
 162                         uint32_t bytes_per_pixel = drv_bytes_per_pixel_from_format(format, 0);
 163                         width = ALIGN(width, 256 / bytes_per_pixel);
 164                 }
 165
 166                 return dri_bo_create(bo, width, height, format, use_flags);
 167         }
 168
 169         stride = drv_stride_from_format(format, width, 0);
 170         stride = ALIGN(stride,256);
 171
 172         drv_bo_from_format(bo, stride, height, format);
 173
 174         memset(&gem_create, 0, sizeof(gem_create));
 175         gem_create.in.bo_size = bo->total_size;
 176         gem_create.in.alignment = 256;
 177         gem_create.in.domain_flags = 0;
 178
 179         if (use_flags & (BO_USE_LINEAR | BO_USE_SW_MASK))
 180                 gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 181
 182         gem_create.in.domains = AMDGPU_GEM_DOMAIN_GTT;
 183         if (!(use_flags & (BO_USE_SW_READ_OFTEN | BO_USE_SCANOUT)))
 184                 gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 185
 186         /* Allocate the buffer with the preferred heap. */
 187         ret = drmCommandWriteRead(drv_get_fd(bo->drv), DRM_AMDGPU_GEM_CREATE, &gem_create,
 188                                   sizeof(gem_create));
 189         if (ret < 0)
 190                 return ret;
 191
 192         for (plane = 0; plane < bo->num_planes; plane++)
 193                 bo->handles[plane].u32 = gem_create.out.handle;
 194
 195         return 0;
 196 }
 197
 198 static int amdgpu_import_bo(struct bo *bo, struct drv_import_fd_data *data)
 199 {
 200         struct combination *combo;
 201         combo = drv_get_combination(bo->drv, data->format, data->use_flags);
 202         if (!combo)
 203                 return -EINVAL;
 204
 205         if (combo->metadata.tiling == TILE_TYPE_DRI)
 206                 return dri_bo_import(bo, data);
 207         else
 208                 return drv_prime_bo_import(bo, data);
 209 }
 210
 211 static int amdgpu_destroy_bo(struct bo *bo)
 212 {
 213         if (bo->priv)
 214                 return dri_bo_destroy(bo);
 215         else
 216                 return drv_gem_bo_destroy(bo);
 217 }
 218
 219 static void *amdgpu_map_bo(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
 220 {
 221         int ret;
 222         union drm_amdgpu_gem_mmap gem_map;
 223
 224         if (bo->priv)
 225                 return dri_bo_map(bo, vma, plane, map_flags);
 226
 227         memset(&gem_map, 0, sizeof(gem_map));
 228         gem_map.in.handle = bo->handles[plane].u32;
 229
 230         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_AMDGPU_GEM_MMAP, &gem_map);
 231         if (ret) {
 232                 drv_log("DRM_IOCTL_AMDGPU_GEM_MMAP failed\n");
 233                 return MAP_FAILED;
 234         }
 235
 236         vma->length = bo->total_size;
 237
 238         return mmap(0, bo->total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
 239                     gem_map.out.addr_ptr);
 240 }
 241
 242 static int amdgpu_unmap_bo(struct bo *bo, struct vma *vma)
 243 {
 244         if (bo->priv)
 245                 return dri_bo_unmap(bo, vma);
 246         else
 247                 return munmap(vma->addr, vma->length);
 248 }
 249
 250 static int amdgpu_bo_invalidate(struct bo *bo, struct mapping *mapping)
 251 {
 252         int ret;
 253         union drm_amdgpu_gem_wait_idle wait_idle;
 254
 255         if (bo->priv)
 256                 return 0;
 257
 258         memset(&wait_idle, 0, sizeof(wait_idle));
 259         wait_idle.in.handle = bo->handles[0].u32;
 260         wait_idle.in.timeout = AMDGPU_TIMEOUT_INFINITE;
 261
 262         ret = drmCommandWriteRead(bo->drv->fd, DRM_AMDGPU_GEM_WAIT_IDLE, &wait_idle,
 263                                   sizeof(wait_idle));
 264
 265         if (ret < 0) {
 266                 drv_log("DRM_AMDGPU_GEM_WAIT_IDLE failed with %d\n", ret);
 267                 return ret;
 268         }
 269
 270         if (ret == 0 && wait_idle.out.status)
 271                 drv_log("DRM_AMDGPU_GEM_WAIT_IDLE BO is busy\n");
 272
 273         return 0;
 274 }
 275
 276 static uint32_t amdgpu_resolve_format(uint32_t format, uint64_t use_flags)
 277 {
 278         switch (format) {
 279         case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
 280                 /* Camera subsystem requires NV12. */
 281                 if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
 282                         return DRM_FORMAT_NV12;
 283                 /*HACK: See b/28671744 */
 284                 return DRM_FORMAT_XBGR8888;
 285         case DRM_FORMAT_FLEX_YCbCr_420_888:
 286                 return DRM_FORMAT_NV12;
 287         default:
 288                 return format;
 289         }
 290 }
 291
 292 const struct backend backend_amdgpu = {
 293         .name = "amdgpu",
 294         .init = amdgpu_init,
 295         .close = amdgpu_close,
 296         .bo_create = amdgpu_create_bo,
 297         .bo_destroy = amdgpu_destroy_bo,
 298         .bo_import = amdgpu_import_bo,
 299         .bo_map = amdgpu_map_bo,
 300         .bo_unmap = amdgpu_unmap_bo,
 301         .bo_invalidate = amdgpu_bo_invalidate,
 302         .resolve_format = amdgpu_resolve_format,
 303 };
 304
 305 #endif