i915: Always set the modifier when allocating BOs

[android-x86/external-minigbm.git] / amdgpu.c

diff --git a/amdgpu.c b/amdgpu.c
index d91006d..cca3537 100644 (file)
--- a/amdgpu.c
+++ b/amdgpu.c
@@ -273,7 +273,6 @@ static void *amdgpu_addrlib_init(int fd)
 
 static int amdgpu_init(struct driver *drv)
 {
-       int ret;
        void *addrlib;
        struct format_metadata metadata;
        uint64_t use_flags = BO_USE_RENDER_MASK;
@@ -284,10 +283,18 @@ static int amdgpu_init(struct driver *drv)
 
        drv->priv = addrlib;
 
-       ret = drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
-                                  &LINEAR_METADATA, BO_USE_TEXTURE_MASK);
-       if (ret)
-               return ret;
+       drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
+                            &LINEAR_METADATA, BO_USE_TEXTURE_MASK);
+
+       /* YUV format for camera */
+       drv_modify_combination(drv, DRM_FORMAT_NV12, &LINEAR_METADATA,
+                              BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
+       /*
+        * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots
+        * from camera.
+        */
+       drv_modify_combination(drv, DRM_FORMAT_R8, &LINEAR_METADATA,
+                              BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
 
        drv_modify_combination(drv, DRM_FORMAT_NV21, &LINEAR_METADATA, BO_USE_SCANOUT);
        drv_modify_combination(drv, DRM_FORMAT_NV12, &LINEAR_METADATA, BO_USE_SCANOUT);
@@ -296,10 +303,8 @@ static int amdgpu_init(struct driver *drv)
        metadata.priority = 2;
        metadata.modifier = DRM_FORMAT_MOD_LINEAR;
 
-       ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
-                                  &metadata, use_flags);
-       if (ret)
-               return ret;
+       drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
+                            &metadata, use_flags);
 
        drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
        drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
@@ -309,10 +314,8 @@ static int amdgpu_init(struct driver *drv)
        metadata.priority = 3;
        metadata.modifier = DRM_FORMAT_MOD_LINEAR;
 
-       ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
-                                  &metadata, use_flags);
-       if (ret)
-               return ret;
+       drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
+                            &metadata, use_flags);
 
        use_flags &= ~BO_USE_SW_WRITE_OFTEN;
        use_flags &= ~BO_USE_SW_READ_OFTEN;
@@ -321,10 +324,8 @@ static int amdgpu_init(struct driver *drv)
        metadata.tiling = ADDR_DISPLAYABLE << 16 | ADDR_TM_2D_TILED_THIN1;
        metadata.priority = 4;
 
-       ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
-                                  &metadata, use_flags);
-       if (ret)
-               return ret;
+       drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
+                            &metadata, use_flags);
 
        drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_SCANOUT);
        drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_SCANOUT);
@@ -333,12 +334,10 @@ static int amdgpu_init(struct driver *drv)
        metadata.tiling = ADDR_NON_DISPLAYABLE << 16 | ADDR_TM_2D_TILED_THIN1;
        metadata.priority = 5;
 
-       ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
-                                  &metadata, use_flags);
-       if (ret)
-               return ret;
+       drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
+                            &metadata, use_flags);
 
-       return ret;
+       return 0;
 }
 
 static void amdgpu_close(struct driver *drv)
@@ -377,8 +376,20 @@ static int amdgpu_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint
        gem_create.in.bo_size = bo->total_size;
        gem_create.in.alignment = addr_out.baseAlign;
        /* Set the placement. */
-       gem_create.in.domains = AMDGPU_GEM_DOMAIN_VRAM;
-       gem_create.in.domain_flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
+
+       gem_create.in.domain_flags = 0;
+       if (use_flags & (BO_USE_LINEAR | BO_USE_SW))
+               gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
+
+       if (use_flags & (BO_USE_SCANOUT | BO_USE_CURSOR)) {
+               /* TODO(dbehr) do not use VRAM after we enable display VM */
+               gem_create.in.domains = AMDGPU_GEM_DOMAIN_VRAM;
+       } else {
+               gem_create.in.domains = AMDGPU_GEM_DOMAIN_GTT;
+               if (!(use_flags & BO_USE_SW_READ_OFTEN))
+                       gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_CPU_GTT_USWC;
+       }
+
        /* Allocate the buffer with the preferred heap. */
        ret = drmCommandWriteRead(drv_get_fd(bo->drv), DRM_AMDGPU_GEM_CREATE, &gem_create,
                                  sizeof(gem_create));
@@ -396,7 +407,7 @@ static int amdgpu_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint
        return ret;
 }
 
-static void *amdgpu_bo_map(struct bo *bo, struct map_info *data, size_t plane, uint32_t map_flags)
+static void *amdgpu_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
 {
        int ret;
        union drm_amdgpu_gem_mmap gem_map;
@@ -410,7 +421,7 @@ static void *amdgpu_bo_map(struct bo *bo, struct map_info *data, size_t plane, u
                return MAP_FAILED;
        }
 
-       data->length = bo->total_size;
+       vma->length = bo->total_size;
 
        return mmap(0, bo->total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
                    gem_map.out.addr_ptr);
@@ -419,6 +430,12 @@ static void *amdgpu_bo_map(struct bo *bo, struct map_info *data, size_t plane, u
 static uint32_t amdgpu_resolve_format(uint32_t format, uint64_t use_flags)
 {
        switch (format) {
+       case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
+               /* Camera subsystem requires NV12. */
+               if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
+                       return DRM_FORMAT_NV12;
+               /*HACK: See b/28671744 */
+               return DRM_FORMAT_XBGR8888;
        case DRM_FORMAT_FLEX_YCbCr_420_888:
                return DRM_FORMAT_NV12;
        default:
@@ -426,7 +443,7 @@ static uint32_t amdgpu_resolve_format(uint32_t format, uint64_t use_flags)
        }
 }
 
-struct backend backend_amdgpu = {
+const struct backend backend_amdgpu = {
        .name = "amdgpu",
        .init = amdgpu_init,
        .close = amdgpu_close,