Use drm gem acess userdata IOCTL for set/get interlace

[android-x86/external-minigbm.git] / cros_gralloc / i915_private_android_types.h

diff --git a/cros_gralloc/i915_private_android_types.h b/cros_gralloc/i915_private_android_types.h
index e756ca1..4ed993c 100644 (file)
--- a/cros_gralloc/i915_private_android_types.h
+++ b/cros_gralloc/i915_private_android_types.h
@@ -67,6 +67,9 @@ enum { HAL_PIXEL_FORMAT_NV12_Y_TILED_INTEL = 0x100,
 enum { GRALLOC1_FUNCTION_SET_MODIFIER = 101,
        GRALLOC1_FUNCTION_GET_BYTE_STRIDE = 102,
        GRALLOC1_FUNCTION_GET_PRIME = 103,
+       GRALLOC1_FUNCTION_SET_INTERLACE = 104,
+       GRALLOC1_FUNCTION_SET_PROTECTIONINFO = 105,
+       GRALLOC1_FUNCTION_GET_INTERLACE = 106,
        GRALLOC1_LAST_CUSTOM = 500 };
 
 typedef int32_t /*gralloc1_error_t*/ (*GRALLOC1_PFN_SET_MODIFIER)(
@@ -77,6 +80,28 @@ typedef int32_t /*gralloc1_error_t*/ (*GRALLOC1_PFN_GET_BYTE_STRIDE)(
 
 typedef int32_t /*gralloc1_error_t*/ (*GRALLOC1_PFN_GET_PRIME)(
         gralloc1_device_t *device, buffer_handle_t buffer, uint32_t *prime);
+
+typedef int32_t /*gralloc1_error_t*/ (*GRALLOC1_PFN_SET_INTERLACE)(gralloc1_device_t *device,
+                                                                  buffer_handle_t buffer,
+                                                                  uint32_t interlace);
+
+typedef int32_t /*gralloc1_error_t*/ (*GRALLOC1_PFN_GET_INTERLACE)(gralloc1_device_t *device,
+                                                                  buffer_handle_t buffer,
+                                                                  uint32_t *interlace);
+
+typedef int32_t /*gralloc1_error_t*/ (*GRALLOC1_PFN_SET_PROTECTIONINFO)(gralloc1_device_t *device,
+                                                                       buffer_handle_t buffer,
+                                                                       uint32_t protection_info);
+
+typedef union intel_protection_info_type_t {
+       uint32_t value;
+       struct {
+           uint32_t is_encrypted  : 8;
+           uint32_t pavp_sesion_id : 8;
+           uint32_t pavp_instance_id: 16;
+       };
+}intel_protection_info_type_t;
+
 #endif
 
 #endif