#include <assert.h>
#include <errno.h>
-#include <i915_drm.h>
#include <stdbool.h>
#include <stdio.h>
#include <string.h>
#include <xf86drm.h>
#include "drv_priv.h"
+#include "external/i915_drm.h"
#include "helpers.h"
#include "util.h"
static const uint32_t texture_only_formats[] = { DRM_FORMAT_R8, DRM_FORMAT_NV12, DRM_FORMAT_P010,
DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID };
+static const uint64_t gen_modifier_order[] = { I915_FORMAT_MOD_Y_TILED, I915_FORMAT_MOD_X_TILED,
+ DRM_FORMAT_MOD_LINEAR };
+
+static const uint64_t gen11_modifier_order[] = { I915_FORMAT_MOD_Y_TILED_CCS,
+ I915_FORMAT_MOD_Y_TILED, I915_FORMAT_MOD_X_TILED,
+ DRM_FORMAT_MOD_LINEAR };
+
+struct modifier_support_t {
+ const uint64_t *order;
+ uint32_t count;
+};
+
struct i915_device {
uint32_t gen;
int32_t has_llc;
+ int32_t has_hw_protection;
+ struct modifier_support_t modifier;
};
static uint32_t i915_get_gen(int device_id)
{
const uint16_t gen3_ids[] = { 0x2582, 0x2592, 0x2772, 0x27A2, 0x27AE,
0x29C2, 0x29B2, 0x29D2, 0xA001, 0xA011 };
+ const uint16_t gen11_ids[] = { 0x4E71, 0x4E61, 0x4E51, 0x4E55, 0x4E57 };
+ const uint16_t gen12_ids[] = { 0x9A40, 0x9A49, 0x9A59, 0x9A60, 0x9A68, 0x9A70,
+ 0x9A78, 0x9AC0, 0x9AC9, 0x9AD9, 0x9AF8 };
unsigned i;
for (i = 0; i < ARRAY_SIZE(gen3_ids); i++)
if (gen3_ids[i] == device_id)
return 3;
+ /* Gen 11 */
+ for (i = 0; i < ARRAY_SIZE(gen11_ids); i++)
+ if (gen11_ids[i] == device_id)
+ return 11;
+
+ /* Gen 12 */
+ for (i = 0; i < ARRAY_SIZE(gen12_ids); i++)
+ if (gen12_ids[i] == device_id)
+ return 12;
return 4;
}
+static void i915_get_modifier_order(struct i915_device *i915)
+{
+ if (i915->gen == 11) {
+ i915->modifier.order = gen11_modifier_order;
+ i915->modifier.count = ARRAY_SIZE(gen11_modifier_order);
+ } else {
+ i915->modifier.order = gen_modifier_order;
+ i915->modifier.count = ARRAY_SIZE(gen_modifier_order);
+ }
+}
+
static uint64_t unset_flags(uint64_t current_flags, uint64_t mask)
{
uint64_t value = current_flags & ~mask;
static int i915_add_combinations(struct driver *drv)
{
struct format_metadata metadata;
- uint64_t render, scanout_and_render, texture_only;
+ uint64_t render, scanout_and_render, texture_only, hw_protected;
+ struct i915_device *i915 = drv->priv;
scanout_and_render = BO_USE_RENDER_MASK | BO_USE_SCANOUT;
render = BO_USE_RENDER_MASK;
texture_only = BO_USE_TEXTURE_MASK;
- uint64_t linear_mask = BO_USE_RENDERSCRIPT | BO_USE_LINEAR | BO_USE_PROTECTED |
- BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN;
+ // HW protected buffers also need to be scanned out.
+ hw_protected = i915->has_hw_protection ? (BO_USE_PROTECTED | BO_USE_SCANOUT) : 0;
+
+ uint64_t linear_mask =
+ BO_USE_RENDERSCRIPT | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN;
metadata.tiling = I915_TILING_NONE;
metadata.priority = 1;
texture_only);
drv_modify_linear_combinations(drv);
- /*
- * Chrome uses DMA-buf mmap to write to YV12 buffers, which are then accessed by the
- * Video Encoder Accelerator (VEA). It could also support NV12 potentially in the future.
- */
- drv_modify_combination(drv, DRM_FORMAT_YVU420, &metadata, BO_USE_HW_VIDEO_ENCODER);
+
+ /* NV12 format for camera, display, decoding and encoding. */
/* IPU3 camera ISP supports only NV12 output. */
drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata,
- BO_USE_HW_VIDEO_ENCODER | BO_USE_HW_VIDEO_DECODER |
- BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_SCANOUT);
+ BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_SCANOUT |
+ BO_USE_HW_VIDEO_DECODER | BO_USE_HW_VIDEO_ENCODER |
+ hw_protected);
/* Android CTS tests require this. */
drv_add_combination(drv, DRM_FORMAT_BGR888, &metadata, BO_USE_SW_MASK);
/*
* R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots
- * from camera.
+ * from camera and input/output from hardware decoder/encoder.
*/
drv_modify_combination(drv, DRM_FORMAT_R8, &metadata,
- BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
+ BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_HW_VIDEO_DECODER |
+ BO_USE_HW_VIDEO_ENCODER);
render = unset_flags(render, linear_mask);
scanout_and_render = unset_flags(scanout_and_render, linear_mask);
metadata.priority = 3;
metadata.modifier = I915_FORMAT_MOD_Y_TILED;
- scanout_and_render = unset_flags(scanout_and_render, BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY);
+ scanout_and_render =
+ unset_flags(scanout_and_render, BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY);
/* Support y-tiled NV12 and P010 for libva */
#ifdef I915_SCANOUT_Y_TILED
- drv_add_combination(drv, DRM_FORMAT_NV12, &metadata,
- BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER | BO_USE_SCANOUT);
+ uint64_t nv12_usage =
+ BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER | BO_USE_SCANOUT | hw_protected;
+ uint64_t p010_usage = BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER | hw_protected;
#else
- drv_add_combination(drv, DRM_FORMAT_NV12, &metadata,
- BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER);
+ uint64_t nv12_usage = BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER;
+ uint64_t p010_usage = nv12_usage;
#endif
+ drv_add_combination(drv, DRM_FORMAT_NV12, &metadata, nv12_usage);
+ drv_add_combination(drv, DRM_FORMAT_P010, &metadata, p010_usage);
+
scanout_and_render = unset_flags(scanout_and_render, BO_USE_SCANOUT);
- drv_add_combination(drv, DRM_FORMAT_P010, &metadata,
- BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER);
drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render);
drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
* horizontal alignment so that row start on a cache line (64
* bytes).
*/
+#ifdef LINEAR_ALIGN_256
+ /*
+ * If we want to import these buffers to amdgpu they need to
+ * their match LINEAR_ALIGNED requirement of 256 byte alignement.
+ */
+ horizontal_alignment = 256;
+#else
horizontal_alignment = 64;
+#endif
vertical_alignment = 4;
break;
int ret;
int device_id;
struct i915_device *i915;
- drm_i915_getparam_t get_param;
+ drm_i915_getparam_t get_param = { 0 };
i915 = calloc(1, sizeof(*i915));
if (!i915)
return -ENOMEM;
- memset(&get_param, 0, sizeof(get_param));
get_param.param = I915_PARAM_CHIPSET_ID;
get_param.value = &device_id;
ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
}
i915->gen = i915_get_gen(device_id);
+ i915_get_modifier_order(i915);
memset(&get_param, 0, sizeof(get_param));
get_param.param = I915_PARAM_HAS_LLC;
return -EINVAL;
}
- drv->priv = i915;
+ if (i915->gen >= 12)
+ i915->has_hw_protection = 1;
+ drv->priv = i915;
return i915_add_combinations(drv);
}
static int i915_bo_compute_metadata(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
uint64_t use_flags, const uint64_t *modifiers, uint32_t count)
{
- static const uint64_t modifier_order[] = {
- I915_FORMAT_MOD_Y_TILED_CCS,
- I915_FORMAT_MOD_Y_TILED,
- I915_FORMAT_MOD_X_TILED,
- DRM_FORMAT_MOD_LINEAR,
- };
uint64_t modifier;
+ struct i915_device *i915 = bo->drv->priv;
+ bool huge_bo = (i915->gen < 11) && (width > 4096);
if (modifiers) {
modifier =
- drv_pick_modifier(modifiers, count, modifier_order, ARRAY_SIZE(modifier_order));
+ drv_pick_modifier(modifiers, count, i915->modifier.order, i915->modifier.count);
} else {
struct combination *combo = drv_get_combination(bo->drv, format, use_flags);
if (!combo)
modifier = combo->metadata.modifier;
}
+ /*
+ * i915 only supports linear/x-tiled above 4096 wide on Gen9/Gen10 GPU.
+ * VAAPI decode in NV12 Y tiled format so skip modifier change for NV12/P010 huge bo.
+ */
+ if (huge_bo && format != DRM_FORMAT_NV12 && format != DRM_FORMAT_P010 &&
+ modifier != I915_FORMAT_MOD_X_TILED && modifier != DRM_FORMAT_MOD_LINEAR) {
+ uint32_t i;
+ for (i = 0; modifiers && i < count; i++) {
+ if (modifiers[i] == I915_FORMAT_MOD_X_TILED)
+ break;
+ }
+ if (i == count)
+ modifier = DRM_FORMAT_MOD_LINEAR;
+ else
+ modifier = I915_FORMAT_MOD_X_TILED;
+ }
+
+ /*
+ * Skip I915_FORMAT_MOD_Y_TILED_CCS modifier if compression is disabled
+ * Pick y tiled modifier if it has been passed in, otherwise use linear
+ */
+ if (!bo->drv->compression && modifier == I915_FORMAT_MOD_Y_TILED_CCS) {
+ uint32_t i;
+ for (i = 0; modifiers && i < count; i++) {
+ if (modifiers[i] == I915_FORMAT_MOD_Y_TILED)
+ break;
+ }
+ if (i == count)
+ modifier = DRM_FORMAT_MOD_LINEAR;
+ else
+ modifier = I915_FORMAT_MOD_Y_TILED;
+ }
+
switch (modifier) {
case DRM_FORMAT_MOD_LINEAR:
bo->meta.tiling = I915_TILING_NONE;
{
int ret;
size_t plane;
- struct drm_i915_gem_create gem_create;
- struct drm_i915_gem_set_tiling gem_set_tiling;
+ uint32_t gem_handle;
+ struct drm_i915_gem_set_tiling gem_set_tiling = { 0 };
+ struct i915_device *i915 = bo->drv->priv;
- memset(&gem_create, 0, sizeof(gem_create));
- gem_create.size = bo->meta.total_size;
+ if (i915->has_hw_protection && (bo->meta.use_flags & BO_USE_PROTECTED)) {
+ struct drm_i915_gem_object_param protected_param = {
+ .param = I915_OBJECT_PARAM | I915_PARAM_PROTECTED_CONTENT,
+ .data = 1,
+ };
- ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create);
- if (ret) {
- drv_log("DRM_IOCTL_I915_GEM_CREATE failed (size=%llu)\n", gem_create.size);
- return -errno;
+ struct drm_i915_gem_create_ext_setparam setparam_protected = {
+ .base = { .name = I915_GEM_CREATE_EXT_SETPARAM },
+ .param = protected_param,
+ };
+
+ struct drm_i915_gem_create_ext create_ext = {
+ .size = bo->meta.total_size,
+ .extensions = (uintptr_t)&setparam_protected,
+ };
+
+ ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext);
+ if (ret) {
+ drv_log("DRM_IOCTL_I915_GEM_CREATE_EXT failed (size=%llu)\n",
+ create_ext.size);
+ return -errno;
+ }
+
+ gem_handle = create_ext.handle;
+ } else {
+ struct drm_i915_gem_create gem_create = { 0 };
+ gem_create.size = bo->meta.total_size;
+ ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create);
+ if (ret) {
+ drv_log("DRM_IOCTL_I915_GEM_CREATE failed (size=%llu)\n", gem_create.size);
+ return -errno;
+ }
+
+ gem_handle = gem_create.handle;
}
for (plane = 0; plane < bo->meta.num_planes; plane++)
- bo->handles[plane].u32 = gem_create.handle;
+ bo->handles[plane].u32 = gem_handle;
- memset(&gem_set_tiling, 0, sizeof(gem_set_tiling));
gem_set_tiling.handle = bo->handles[0].u32;
gem_set_tiling.tiling_mode = bo->meta.tiling;
gem_set_tiling.stride = bo->meta.strides[0];
ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_TILING, &gem_set_tiling);
if (ret) {
- struct drm_gem_close gem_close;
- memset(&gem_close, 0, sizeof(gem_close));
+ struct drm_gem_close gem_close = { 0 };
gem_close.handle = bo->handles[0].u32;
drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
static int i915_bo_import(struct bo *bo, struct drv_import_fd_data *data)
{
int ret;
- struct drm_i915_gem_get_tiling gem_get_tiling;
+ struct drm_i915_gem_get_tiling gem_get_tiling = { 0 };
ret = drv_prime_bo_import(bo, data);
if (ret)
return ret;
/* TODO(gsingh): export modifiers and get rid of backdoor tiling. */
- memset(&gem_get_tiling, 0, sizeof(gem_get_tiling));
gem_get_tiling.handle = bo->handles[0].u32;
ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_GET_TILING, &gem_get_tiling);
static void *i915_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
{
int ret;
- void *addr;
+ void *addr = MAP_FAILED;
if (bo->meta.format_modifiers[0] == I915_FORMAT_MOD_Y_TILED_CCS)
return MAP_FAILED;
if (bo->meta.tiling == I915_TILING_NONE) {
- struct drm_i915_gem_mmap gem_map;
- memset(&gem_map, 0, sizeof(gem_map));
-
+ struct drm_i915_gem_mmap gem_map = { 0 };
/* TODO(b/118799155): We don't seem to have a good way to
* detect the use cases for which WC mapping is really needed.
* The current heuristic seems overly coarse and may be slowing
gem_map.size = bo->meta.total_size;
ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP, &gem_map);
- if (ret) {
- drv_log("DRM_IOCTL_I915_GEM_MMAP failed\n");
- return MAP_FAILED;
- }
+ /* DRM_IOCTL_I915_GEM_MMAP mmaps the underlying shm
+ * file and returns a user space address directly, ie,
+ * doesn't go through mmap. If we try that on a
+ * dma-buf that doesn't have a shm file, i915.ko
+ * returns ENXIO. Fall through to
+ * DRM_IOCTL_I915_GEM_MMAP_GTT in that case, which
+ * will mmap on the drm fd instead. */
+ if (ret == 0)
+ addr = (void *)(uintptr_t)gem_map.addr_ptr;
+ }
- addr = (void *)(uintptr_t)gem_map.addr_ptr;
- } else {
- struct drm_i915_gem_mmap_gtt gem_map;
- memset(&gem_map, 0, sizeof(gem_map));
+ if (addr == MAP_FAILED) {
+ struct drm_i915_gem_mmap_gtt gem_map = { 0 };
gem_map.handle = bo->handles[0].u32;
-
ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &gem_map);
if (ret) {
drv_log("DRM_IOCTL_I915_GEM_MMAP_GTT failed\n");
static int i915_bo_invalidate(struct bo *bo, struct mapping *mapping)
{
int ret;
- struct drm_i915_gem_set_domain set_domain;
+ struct drm_i915_gem_set_domain set_domain = { 0 };
- memset(&set_domain, 0, sizeof(set_domain));
set_domain.handle = bo->handles[0].u32;
if (bo->meta.tiling == I915_TILING_NONE) {
set_domain.read_domains = I915_GEM_DOMAIN_CPU;
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