#include <errno.h>
#include <i915_drm.h>
-#include <intel_bufmgr.h>
+#include <stdio.h>
#include <string.h>
#include <sys/mman.h>
#include <xf86drm.h>
#include "helpers.h"
#include "util.h"
-static const uint32_t tileable_formats[] = { DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR8888,
- DRM_FORMAT_ARGB8888, DRM_FORMAT_RGB565,
- DRM_FORMAT_XBGR8888, DRM_FORMAT_XRGB1555,
- DRM_FORMAT_XRGB8888, DRM_FORMAT_UYVY,
- DRM_FORMAT_YUYV };
+#define I915_CACHELINE_SIZE 64
+#define I915_CACHELINE_MASK (I915_CACHELINE_SIZE - 1)
-static const uint32_t linear_only_formats[] = { DRM_FORMAT_GR88, DRM_FORMAT_R8, DRM_FORMAT_YVU420,
- DRM_FORMAT_YVU420_ANDROID };
+static const uint32_t render_target_formats[] = { DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_ARGB8888, DRM_FORMAT_RGB565,
+ DRM_FORMAT_XBGR8888, DRM_FORMAT_XRGB1555,
+ DRM_FORMAT_XRGB8888 };
-struct i915_device {
- int gen;
- drm_intel_bufmgr *mgr;
- uint32_t count;
-};
+static const uint32_t tileable_texture_source_formats[] = { DRM_FORMAT_GR88, DRM_FORMAT_NV12,
+ DRM_FORMAT_R8, DRM_FORMAT_UYVY,
+ DRM_FORMAT_YUYV };
-struct i915_bo {
- drm_intel_bo *ibos[DRV_MAX_PLANES];
+static const uint32_t texture_source_formats[] = { DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID };
+
+struct i915_device {
+ uint32_t gen;
+ int32_t has_llc;
};
-static int get_gen(int device_id)
+static uint32_t i915_get_gen(int device_id)
{
const uint16_t gen3_ids[] = { 0x2582, 0x2592, 0x2772, 0x27A2, 0x27AE,
0x29C2, 0x29B2, 0x29D2, 0xA001, 0xA011 };
*/
for (i = 0; i < drv->backend->combos.size; i++) {
combo = &drv->backend->combos.data[i];
- if (combo->format == item->format) {
- if ((combo->metadata.tiling == I915_TILING_Y &&
- item->modifier == I915_FORMAT_MOD_Y_TILED) ||
- (combo->metadata.tiling == I915_TILING_X &&
- item->modifier == I915_FORMAT_MOD_X_TILED)) {
- combo->metadata.modifier = item->modifier;
- combo->usage |= item->usage;
- } else if (combo->metadata.tiling != I915_TILING_Y) {
- combo->usage |= item->usage;
- }
+ if (combo->format != item->format)
+ continue;
+
+ if (item->modifier == DRM_FORMAT_MOD_NONE &&
+ combo->metadata.tiling == I915_TILING_X) {
+ /*
+ * FIXME: drv_query_kms() does not report the available modifiers
+ * yet, but we know that all hardware can scanout from X-tiled
+ * buffers, so let's add this to our combinations, except for
+ * cursor, which must not be tiled.
+ */
+ combo->usage |= item->usage & ~BO_USE_CURSOR;
}
+
+ if (combo->metadata.modifier == item->modifier)
+ combo->usage |= item->usage;
}
return 0;
uint32_t i, num_items;
struct kms_item *items;
struct format_metadata metadata;
- uint64_t flags = BO_COMMON_USE_MASK;
+ uint64_t render_flags, texture_flags;
+
+ render_flags = BO_USE_RENDER_MASK;
+ texture_flags = BO_USE_TEXTURE_MASK;
metadata.tiling = I915_TILING_NONE;
metadata.priority = 1;
metadata.modifier = DRM_FORMAT_MOD_NONE;
- ret = drv_add_combinations(drv, linear_only_formats, ARRAY_SIZE(linear_only_formats),
- &metadata, flags);
+ ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
+ &metadata, render_flags);
if (ret)
return ret;
- ret = drv_add_combinations(drv, tileable_formats, ARRAY_SIZE(tileable_formats), &metadata,
- flags);
+ ret = drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
+ &metadata, texture_flags);
+ if (ret)
+ return ret;
+
+ ret = drv_add_combinations(drv, tileable_texture_source_formats,
+ ARRAY_SIZE(tileable_texture_source_formats), &metadata,
+ texture_flags);
if (ret)
return ret;
drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
- flags &= ~BO_USE_SW_WRITE_OFTEN;
- flags &= ~BO_USE_SW_READ_OFTEN;
- flags &= ~BO_USE_LINEAR;
+ /* IPU3 camera ISP supports only NV12 output. */
+ drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata,
+ BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
+ /*
+ * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots
+ * from camera.
+ */
+ drv_modify_combination(drv, DRM_FORMAT_R8, &metadata,
+ BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
+
+ render_flags &= ~BO_USE_RENDERSCRIPT;
+ render_flags &= ~BO_USE_SW_WRITE_OFTEN;
+ render_flags &= ~BO_USE_SW_READ_OFTEN;
+ render_flags &= ~BO_USE_LINEAR;
+
+ texture_flags &= ~BO_USE_RENDERSCRIPT;
+ texture_flags &= ~BO_USE_SW_WRITE_OFTEN;
+ texture_flags &= ~BO_USE_SW_READ_OFTEN;
+ texture_flags &= ~BO_USE_LINEAR;
metadata.tiling = I915_TILING_X;
metadata.priority = 2;
+ metadata.modifier = I915_FORMAT_MOD_X_TILED;
- ret = drv_add_combinations(drv, tileable_formats, ARRAY_SIZE(tileable_formats), &metadata,
- flags);
+ ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
+ &metadata, render_flags);
+ if (ret)
+ return ret;
+
+ ret = drv_add_combinations(drv, tileable_texture_source_formats,
+ ARRAY_SIZE(tileable_texture_source_formats), &metadata,
+ texture_flags);
if (ret)
return ret;
metadata.tiling = I915_TILING_Y;
metadata.priority = 3;
+ metadata.modifier = I915_FORMAT_MOD_Y_TILED;
+
+ ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
+ &metadata, render_flags);
+ if (ret)
+ return ret;
- ret = drv_add_combinations(drv, tileable_formats, ARRAY_SIZE(tileable_formats), &metadata,
- flags);
+ ret = drv_add_combinations(drv, tileable_texture_source_formats,
+ ARRAY_SIZE(tileable_texture_source_formats), &metadata,
+ texture_flags);
if (ret)
return ret;
break;
}
+ /*
+ * The alignment calculated above is based on the full size luma plane and to have chroma
+ * planes properly aligned with subsampled formats, we need to multiply luma alignment by
+ * subsampling factor.
+ */
+ switch (bo->format) {
+ case DRM_FORMAT_YVU420_ANDROID:
+ case DRM_FORMAT_YVU420:
+ horizontal_alignment *= 2;
+ /* Fall through */
+ case DRM_FORMAT_NV12:
+ vertical_alignment *= 2;
+ break;
+ }
+
*aligned_height = ALIGN(bo->height, vertical_alignment);
if (i915->gen > 3) {
*stride = ALIGN(*stride, horizontal_alignment);
return 0;
}
+static void i915_clflush(void *start, size_t size)
+{
+ void *p = (void *)(((uintptr_t)start) & ~I915_CACHELINE_MASK);
+ void *end = (void *)((uintptr_t)start + size);
+
+ __builtin_ia32_mfence();
+ while (p < end) {
+ __builtin_ia32_clflush(p);
+ p = (void *)((uintptr_t)p + I915_CACHELINE_SIZE);
+ }
+}
+
static int i915_init(struct driver *drv)
{
- struct i915_device *i915_dev;
- drm_i915_getparam_t get_param;
- int device_id;
int ret;
+ int device_id;
+ struct i915_device *i915;
+ drm_i915_getparam_t get_param;
- i915_dev = calloc(1, sizeof(*i915_dev));
- if (!i915_dev)
- return -1;
+ i915 = calloc(1, sizeof(*i915));
+ if (!i915)
+ return -ENOMEM;
memset(&get_param, 0, sizeof(get_param));
get_param.param = I915_PARAM_CHIPSET_ID;
get_param.value = &device_id;
ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
if (ret) {
- fprintf(stderr, "drv: DRM_IOCTL_I915_GETPARAM failed\n");
- free(i915_dev);
+ fprintf(stderr, "drv: Failed to get I915_PARAM_CHIPSET_ID\n");
+ free(i915);
return -EINVAL;
}
- i915_dev->gen = get_gen(device_id);
- i915_dev->count = 0;
+ i915->gen = i915_get_gen(device_id);
- i915_dev->mgr = drm_intel_bufmgr_gem_init(drv->fd, 16 * 1024);
- if (!i915_dev->mgr) {
- fprintf(stderr, "drv: drm_intel_bufmgr_gem_init failed\n");
- free(i915_dev);
+ memset(&get_param, 0, sizeof(get_param));
+ get_param.param = I915_PARAM_HAS_LLC;
+ get_param.value = &i915->has_llc;
+ ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
+ if (ret) {
+ fprintf(stderr, "drv: Failed to get I915_PARAM_HAS_LLC\n");
+ free(i915);
return -EINVAL;
}
- drv->priv = i915_dev;
+ drv->priv = i915;
return i915_add_combinations(drv);
}
-static void i915_close(struct driver *drv)
-{
- struct i915_device *i915_dev = drv->priv;
- drm_intel_bufmgr_destroy(i915_dev->mgr);
- free(i915_dev);
- drv->priv = NULL;
-}
-
static int i915_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
uint32_t flags)
{
int ret;
size_t plane;
- char name[20];
uint32_t stride;
- uint32_t tiling_mode;
- struct i915_bo *i915_bo;
+ struct drm_i915_gem_create gem_create;
+ struct drm_i915_gem_set_tiling gem_set_tiling;
+ struct combination *combo;
- stride = drv_stride_from_format(format, width, 0);
- struct i915_device *i915_dev = (struct i915_device *)bo->drv->priv;
+ combo = drv_get_combination(bo->drv, format, flags);
+ if (!combo)
+ return -EINVAL;
- if (flags & (BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN))
- tiling_mode = I915_TILING_NONE;
- else if (flags & BO_USE_SCANOUT)
- tiling_mode = I915_TILING_X;
- else
- tiling_mode = I915_TILING_Y;
+ bo->tiling = combo->metadata.tiling;
- /*
- * Align the Y plane to 128 bytes so the chroma planes would be aligned
- * to 64 byte boundaries. This is an Intel HW requirement.
- */
- if (format == DRM_FORMAT_YVU420 || format == DRM_FORMAT_YVU420_ANDROID) {
- stride = ALIGN(stride, 128);
- tiling_mode = I915_TILING_NONE;
- }
+ stride = drv_stride_from_format(format, width, 0);
- ret = i915_align_dimensions(bo, tiling_mode, &stride, &height);
+ ret = i915_align_dimensions(bo, bo->tiling, &stride, &height);
if (ret)
return ret;
- drv_bo_from_format(bo, stride, height, format);
-
- snprintf(name, sizeof(name), "i915-buffer-%u", i915_dev->count);
- i915_dev->count++;
+ /*
+ * HAL_PIXEL_FORMAT_YV12 requires the buffer height not be aligned, but we need to keep
+ * total size as with aligned height to ensure enough padding space after each plane to
+ * satisfy GPU alignment requirements.
+ *
+ * We do it by first calling drv_bo_from_format() with aligned height and
+ * DRM_FORMAT_YVU420, which allows height alignment, saving the total size it calculates
+ * and then calling it again with requested parameters.
+ *
+ * This relies on the fact that i965 driver uses separate surfaces for each plane and
+ * contents of padding bytes is not affected, as it is only used to satisfy GPU cache
+ * requests.
+ *
+ * This is enforced by Mesa in src/intel/isl/isl_gen8.c, inside
+ * isl_gen8_choose_image_alignment_el(), which is used for GEN9 and GEN8.
+ */
+ if (format == DRM_FORMAT_YVU420_ANDROID) {
+ uint32_t unaligned_height = bo->height;
+ size_t total_size;
+
+ drv_bo_from_format(bo, stride, height, DRM_FORMAT_YVU420);
+ total_size = bo->total_size;
+ drv_bo_from_format(bo, stride, unaligned_height, format);
+ bo->total_size = total_size;
+ } else {
+ drv_bo_from_format(bo, stride, height, format);
+ }
- i915_bo = calloc(1, sizeof(*i915_bo));
- if (!i915_bo)
- return -ENOMEM;
+ /*
+ * Quoting Mesa ISL library:
+ *
+ * - For linear surfaces, additional padding of 64 bytes is required at
+ * the bottom of the surface. This is in addition to the padding
+ * required above.
+ */
+ if (bo->tiling == I915_TILING_NONE)
+ bo->total_size += 64;
- bo->priv = i915_bo;
+ memset(&gem_create, 0, sizeof(gem_create));
+ gem_create.size = bo->total_size;
- i915_bo->ibos[0] = drm_intel_bo_alloc(i915_dev->mgr, name, bo->total_size, 0);
- if (!i915_bo->ibos[0]) {
- fprintf(stderr, "drv: drm_intel_bo_alloc failed");
- free(i915_bo);
- bo->priv = NULL;
- return -ENOMEM;
+ ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create);
+ if (ret) {
+ fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_CREATE failed (size=%llu)\n",
+ gem_create.size);
+ return ret;
}
- for (plane = 0; plane < bo->num_planes; plane++) {
- if (plane > 0)
- drm_intel_bo_reference(i915_bo->ibos[0]);
-
- bo->handles[plane].u32 = i915_bo->ibos[0]->handle;
- i915_bo->ibos[plane] = i915_bo->ibos[0];
- }
+ for (plane = 0; plane < bo->num_planes; plane++)
+ bo->handles[plane].u32 = gem_create.handle;
- bo->tiling = tiling_mode;
+ memset(&gem_set_tiling, 0, sizeof(gem_set_tiling));
+ gem_set_tiling.handle = bo->handles[0].u32;
+ gem_set_tiling.tiling_mode = bo->tiling;
+ gem_set_tiling.stride = bo->strides[0];
- ret = drm_intel_bo_set_tiling(i915_bo->ibos[0], &bo->tiling, bo->strides[0]);
+ ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_TILING, &gem_set_tiling);
+ if (ret) {
+ struct drm_gem_close gem_close;
+ memset(&gem_close, 0, sizeof(gem_close));
+ gem_close.handle = bo->handles[0].u32;
+ drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
- if (ret || bo->tiling != tiling_mode) {
- fprintf(stderr, "drv: drm_intel_gem_bo_set_tiling failed "
- "errno=%x, stride=%x\n",
- errno, bo->strides[0]);
- /* Calls i915 bo destroy. */
- bo->drv->backend->bo_destroy(bo);
+ fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_SET_TILING failed with %d", errno);
return -errno;
}
return 0;
}
-static int i915_bo_destroy(struct bo *bo)
+static void i915_close(struct driver *drv)
+{
+ free(drv->priv);
+ drv->priv = NULL;
+}
+
+static int i915_bo_import(struct bo *bo, struct drv_import_fd_data *data)
{
- size_t plane;
- struct i915_bo *i915_bo = bo->priv;
+ int ret;
+ struct drm_i915_gem_get_tiling gem_get_tiling;
- for (plane = 0; plane < bo->num_planes; plane++)
- drm_intel_bo_unreference(i915_bo->ibos[plane]);
+ ret = drv_prime_bo_import(bo, data);
+ if (ret)
+ return ret;
+
+ /* TODO(gsingh): export modifiers and get rid of backdoor tiling. */
+ memset(&gem_get_tiling, 0, sizeof(gem_get_tiling));
+ gem_get_tiling.handle = bo->handles[0].u32;
- free(i915_bo);
- bo->priv = NULL;
+ ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_GET_TILING, &gem_get_tiling);
+ if (ret) {
+ drv_gem_bo_destroy(bo);
+ fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_GET_TILING failed.");
+ return ret;
+ }
+ bo->tiling = gem_get_tiling.tiling_mode;
return 0;
}
-static int i915_bo_import(struct bo *bo, struct drv_import_fd_data *data)
+static void *i915_bo_map(struct bo *bo, struct map_info *data, size_t plane, int prot)
{
- size_t plane;
- uint32_t swizzling;
- struct i915_bo *i915_bo;
- struct i915_device *i915_dev = bo->drv->priv;
+ int ret;
+ void *addr;
+ struct drm_i915_gem_set_domain set_domain;
- i915_bo = calloc(1, sizeof(*i915_bo));
- if (!i915_bo)
- return -ENOMEM;
+ memset(&set_domain, 0, sizeof(set_domain));
+ set_domain.handle = bo->handles[0].u32;
+ if (bo->tiling == I915_TILING_NONE) {
+ struct drm_i915_gem_mmap gem_map;
+ memset(&gem_map, 0, sizeof(gem_map));
- bo->priv = i915_bo;
+ gem_map.handle = bo->handles[0].u32;
+ gem_map.offset = 0;
+ gem_map.size = bo->total_size;
- /*
- * When self-importing, libdrm_intel increments the reference count
- * on the drm_intel_bo. It also returns the same drm_intel_bo per GEM
- * handle. Thus, we don't need to increase the reference count
- * (i.e, drv_increment_reference_count) when importing with this
- * backend.
- */
- for (plane = 0; plane < bo->num_planes; plane++) {
+ ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP, &gem_map);
+ if (ret) {
+ fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_MMAP failed\n");
+ return MAP_FAILED;
+ }
- i915_bo->ibos[plane] = drm_intel_bo_gem_create_from_prime(
- i915_dev->mgr, data->fds[plane], data->sizes[plane]);
+ addr = (void *)(uintptr_t)gem_map.addr_ptr;
+ set_domain.read_domains = I915_GEM_DOMAIN_CPU;
+ set_domain.write_domain = I915_GEM_DOMAIN_CPU;
- if (!i915_bo->ibos[plane]) {
- /*
- * Need to call GEM close on planes that were opened,
- * if any. Adjust the num_planes variable to be the
- * plane that failed, so GEM close will be called on
- * planes before that plane.
- */
- bo->num_planes = plane;
- i915_bo_destroy(bo);
- fprintf(stderr, "drv: i915: failed to import failed");
- return -EINVAL;
+ } else {
+ struct drm_i915_gem_mmap_gtt gem_map;
+ memset(&gem_map, 0, sizeof(gem_map));
+
+ gem_map.handle = bo->handles[0].u32;
+
+ ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &gem_map);
+ if (ret) {
+ fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_MMAP_GTT failed\n");
+ return MAP_FAILED;
}
- bo->handles[plane].u32 = i915_bo->ibos[plane]->handle;
+ addr = mmap(0, bo->total_size, prot, MAP_SHARED, bo->drv->fd, gem_map.offset);
+ set_domain.read_domains = I915_GEM_DOMAIN_GTT;
+ set_domain.write_domain = I915_GEM_DOMAIN_GTT;
}
- if (drm_intel_bo_get_tiling(i915_bo->ibos[0], &bo->tiling, &swizzling)) {
- fprintf(stderr, "drv: drm_intel_bo_get_tiling failed");
- i915_bo_destroy(bo);
- return -EINVAL;
+ if (addr == MAP_FAILED) {
+ fprintf(stderr, "drv: i915 GEM mmap failed\n");
+ return addr;
}
- return 0;
-}
-
-static void *i915_bo_map(struct bo *bo, struct map_info *data, size_t plane)
-{
- int ret;
- struct i915_bo *i915_bo = bo->priv;
-
- if (bo->tiling == I915_TILING_NONE)
- /* TODO(gsingh): use bo_map flags to determine if we should
- * enable writing.
- */
- ret = drm_intel_bo_map(i915_bo->ibos[0], 1);
- else
- ret = drm_intel_gem_bo_map_gtt(i915_bo->ibos[0]);
-
+ ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain);
if (ret) {
- fprintf(stderr, "drv: i915_bo_map failed.");
+ fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_SET_DOMAIN failed\n");
return MAP_FAILED;
}
- return i915_bo->ibos[0]->virtual;
+ data->length = bo->total_size;
+ return addr;
}
static int i915_bo_unmap(struct bo *bo, struct map_info *data)
{
- int ret;
- struct i915_bo *i915_bo = bo->priv;
-
- if (bo->tiling == I915_TILING_NONE)
- ret = drm_intel_bo_unmap(i915_bo->ibos[0]);
- else
- ret = drm_intel_gem_bo_unmap_gtt(i915_bo->ibos[0]);
+ struct i915_device *i915 = bo->drv->priv;
+ if (!i915->has_llc && bo->tiling == I915_TILING_NONE)
+ i915_clflush(data->addr, data->length);
- return ret;
+ return munmap(data->addr, data->length);
}
-static uint32_t i915_resolve_format(uint32_t format)
+static uint32_t i915_resolve_format(uint32_t format, uint64_t usage)
{
switch (format) {
case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
+ /* KBL camera subsystem requires NV12. */
+ if (usage & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
+ return DRM_FORMAT_NV12;
/*HACK: See b/28671744 */
return DRM_FORMAT_XBGR8888;
case DRM_FORMAT_FLEX_YCbCr_420_888:
- return DRM_FORMAT_YVU420_ANDROID;
+ /* KBL camera subsystem requires NV12. */
+ if (usage & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
+ return DRM_FORMAT_NV12;
+ return DRM_FORMAT_YVU420;
default:
return format;
}
.init = i915_init,
.close = i915_close,
.bo_create = i915_bo_create,
- .bo_destroy = i915_bo_destroy,
+ .bo_destroy = drv_gem_bo_destroy,
.bo_import = i915_bo_import,
.bo_map = i915_bo_map,
.bo_unmap = i915_bo_unmap,
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