struct tegra_private_map_data {
void *tiled;
void *untiled;
- int prot;
};
static const uint32_t render_target_formats[] = { DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB8888 };
static int tegra_init(struct driver *drv)
{
- int ret;
struct format_metadata metadata;
- uint64_t flags = BO_USE_RENDER_MASK;
+ uint64_t use_flags = BO_USE_RENDER_MASK;
metadata.tiling = NV_MEM_KIND_PITCH;
metadata.priority = 1;
- metadata.modifier = DRM_FORMAT_MOD_NONE;
+ metadata.modifier = DRM_FORMAT_MOD_LINEAR;
- ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
- &metadata, flags);
- if (ret)
- return ret;
+ drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
+ &metadata, use_flags);
drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
- flags &= ~BO_USE_SW_WRITE_OFTEN;
- flags &= ~BO_USE_SW_READ_OFTEN;
- flags &= ~BO_USE_LINEAR;
+ use_flags &= ~BO_USE_SW_WRITE_OFTEN;
+ use_flags &= ~BO_USE_SW_READ_OFTEN;
+ use_flags &= ~BO_USE_LINEAR;
metadata.tiling = NV_MEM_KIND_C32_2CRA;
metadata.priority = 2;
- ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
- &metadata, flags);
- if (ret)
- return ret;
+ drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
+ &metadata, use_flags);
drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_SCANOUT);
drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_SCANOUT);
}
static int tegra_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
- uint32_t flags)
+ uint64_t use_flags)
{
uint32_t size, stride, block_height_log2 = 0;
enum nv_mem_kind kind = NV_MEM_KIND_PITCH;
struct drm_tegra_gem_create gem_create;
int ret;
- if (flags & (BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN))
+ if (use_flags &
+ (BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN))
compute_layout_linear(width, height, format, &stride, &size);
else
compute_layout_blocklinear(width, height, format, &kind, &block_height_log2,
ret = drmIoctl(bo->drv->fd, DRM_IOCTL_TEGRA_GEM_CREATE, &gem_create);
if (ret) {
- fprintf(stderr, "drv: DRM_IOCTL_TEGRA_GEM_CREATE failed (size=%zu)\n", size);
+ drv_log("DRM_IOCTL_TEGRA_GEM_CREATE failed (size=%zu)\n", size);
return ret;
}
return 0;
}
-static void *tegra_bo_map(struct bo *bo, struct map_info *data, size_t plane, int prot)
+static int tegra_bo_import(struct bo *bo, struct drv_import_fd_data *data)
+{
+ int ret;
+ struct drm_tegra_gem_get_tiling gem_get_tiling;
+
+ ret = drv_prime_bo_import(bo, data);
+ if (ret)
+ return ret;
+
+ /* TODO(gsingh): export modifiers and get rid of backdoor tiling. */
+ memset(&gem_get_tiling, 0, sizeof(gem_get_tiling));
+ gem_get_tiling.handle = bo->handles[0].u32;
+
+ ret = drmIoctl(bo->drv->fd, DRM_IOCTL_TEGRA_GEM_GET_TILING, &gem_get_tiling);
+ if (ret) {
+ drv_gem_bo_destroy(bo);
+ return ret;
+ }
+
+ /* NOTE(djmk): we only know about one tiled format, so if our drmIoctl call tells us we are
+ tiled, assume it is this format (NV_MEM_KIND_C32_2CRA) otherwise linear (KIND_PITCH). */
+ if (gem_get_tiling.mode == DRM_TEGRA_GEM_TILING_MODE_PITCH) {
+ bo->tiling = NV_MEM_KIND_PITCH;
+ } else if (gem_get_tiling.mode == DRM_TEGRA_GEM_TILING_MODE_BLOCK) {
+ bo->tiling = NV_MEM_KIND_C32_2CRA;
+ } else {
+ drv_log("%s: unknown tile format %d\n", __func__, gem_get_tiling.mode);
+ drv_gem_bo_destroy(bo);
+ assert(0);
+ }
+
+ bo->format_modifiers[0] = fourcc_mod_code(NV, bo->tiling);
+ return 0;
+}
+
+static void *tegra_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
{
int ret;
struct drm_tegra_gem_mmap gem_map;
ret = drmCommandWriteRead(bo->drv->fd, DRM_TEGRA_GEM_MMAP, &gem_map, sizeof(gem_map));
if (ret < 0) {
- fprintf(stderr, "drv: DRM_TEGRA_GEM_MMAP failed\n");
+ drv_log("DRM_TEGRA_GEM_MMAP failed\n");
return MAP_FAILED;
}
- void *addr = mmap(0, bo->total_size, prot, MAP_SHARED, bo->drv->fd, gem_map.offset);
- data->length = bo->total_size;
+ void *addr = mmap(0, bo->total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
+ gem_map.offset);
+ vma->length = bo->total_size;
if ((bo->tiling & 0xFF) == NV_MEM_KIND_C32_2CRA && addr != MAP_FAILED) {
priv = calloc(1, sizeof(*priv));
priv->untiled = calloc(1, bo->total_size);
priv->tiled = addr;
- priv->prot = prot;
- data->priv = priv;
+ vma->priv = priv;
transfer_tiled_memory(bo, priv->tiled, priv->untiled, TEGRA_READ_TILED_BUFFER);
addr = priv->untiled;
}
return addr;
}
-static int tegra_bo_unmap(struct bo *bo, struct map_info *data)
+static int tegra_bo_unmap(struct bo *bo, struct vma *vma)
{
- if (data->priv) {
- struct tegra_private_map_data *priv = data->priv;
- if (priv->prot & PROT_WRITE)
- transfer_tiled_memory(bo, priv->tiled, priv->untiled,
- TEGRA_WRITE_TILED_BUFFER);
- data->addr = priv->tiled;
+ if (vma->priv) {
+ struct tegra_private_map_data *priv = vma->priv;
+ vma->addr = priv->tiled;
free(priv->untiled);
free(priv);
- data->priv = NULL;
+ vma->priv = NULL;
}
- return munmap(data->addr, data->length);
+ return munmap(vma->addr, vma->length);
}
-static int tegra_bo_import(struct bo *bo, struct drv_import_fd_data *data)
+static int tegra_bo_flush(struct bo *bo, struct mapping *mapping)
{
- int ret;
- struct drm_tegra_gem_get_tiling gem_get_tiling;
+ struct tegra_private_map_data *priv = mapping->vma->priv;
- ret = drv_prime_bo_import(bo, data);
- if (ret)
- return ret;
-
- /* TODO(gsingh): export modifiers and get rid of backdoor tiling. */
- memset(&gem_get_tiling, 0, sizeof(gem_get_tiling));
- gem_get_tiling.handle = bo->handles[0].u32;
+ if (priv && (mapping->vma->map_flags & BO_MAP_WRITE))
+ transfer_tiled_memory(bo, priv->tiled, priv->untiled, TEGRA_WRITE_TILED_BUFFER);
- ret = drmIoctl(bo->drv->fd, DRM_IOCTL_TEGRA_GEM_GET_TILING, &gem_get_tiling);
- if (ret) {
- drv_gem_bo_destroy(bo);
- return ret;
- }
-
- /* NOTE(djmk): we only know about one tiled format, so if our drmIoctl call tells us we are
- tiled, assume it is this format (NV_MEM_KIND_C32_2CRA) otherwise linear (KIND_PITCH). */
- if (gem_get_tiling.mode == DRM_TEGRA_GEM_TILING_MODE_PITCH) {
- bo->tiling = NV_MEM_KIND_PITCH;
- } else if (gem_get_tiling.mode == DRM_TEGRA_GEM_TILING_MODE_BLOCK) {
- bo->tiling = NV_MEM_KIND_C32_2CRA;
- } else {
- fprintf(stderr, "tegra_bo_import: unknown tile format %d", gem_get_tiling.mode);
- drv_gem_bo_destroy(bo);
- assert(0);
- }
-
- bo->format_modifiers[0] = fourcc_mod_code(NV, bo->tiling);
return 0;
}
-struct backend backend_tegra = {
+const struct backend backend_tegra = {
.name = "tegra",
.init = tegra_init,
.bo_create = tegra_bo_create,
.bo_import = tegra_bo_import,
.bo_map = tegra_bo_map,
.bo_unmap = tegra_bo_unmap,
+ .bo_flush = tegra_bo_flush,
};
#endif
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