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(parent: ae1b9f4) | patch
render: clear background using 3D pipeline on GEN8+
authorHaihao Xiang <haihao.xiang@intel.com>
Fri, 1 Jun 2018 04:50:26 +0000 (12:50 +0800)
committerXiang, Haihao <haihao.xiang@intel.com>
Tue, 3 Jul 2018 06:19:04 +0000 (14:19 +0800)
commit3ccc26bc0fdb5b12769c5d2feeafa8fa706a78ba
treeb1f74993fed56672fdb75fc245e6ab1ca770910btree | snapshot
parentae1b9f480a5ed7b8e4ad7cddf5551a2240592f28commit | diff
render: clear background using 3D pipeline on GEN8+

Remove the extra sync between BCS and CS rings

Signed-off-by: Haihao Xiang <haihao.xiang@intel.com>
src/gen8_render.c diff | blob | history
src/gen9_render.c diff | blob | history
src/i965_render.c diff | blob | history
src/i965_render.h diff | blob | history
src/shaders/render/Makefile.am diff | blob | history
src/shaders/render/exa_wm_clear.g7i [new file with mode: 0644] blob
src/shaders/render/exa_wm_clear.g8a [new file with mode: 0644] blob
src/shaders/render/exa_wm_clear.g8b [new file with mode: 0644] blob
src/shaders/render/exa_wm_clear.g9a [new file with mode: 0644] blob
src/shaders/render/exa_wm_clear.g9b [new file with mode: 0644] blob
hardware/intel/common/vaapi
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