ARM: 8265/1: dts: exynos4: Add nodes for L2 cache controller

[android-x86/kernel.git] / arch / arm / boot / dts / exynos4210.dtsi

diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index bcc9e63..8e45ea4 100644 (file)
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -81,6 +81,15 @@
                reg = <0x10023CA0 0x20>;
        };
 
+       l2c: l2-cache-controller@10502000 {
+               compatible = "arm,pl310-cache";
+               reg = <0x10502000 0x1000>;
+               cache-unified;
+               cache-level = <2>;
+               arm,tag-latency = <2 2 1>;
+               arm,data-latency = <2 2 1>;
+       };
+
        gic: interrupt-controller@10490000 {
                cpu-offset = <0x8000>;
        };