staging: rtl8723bs: update to the latest driver

[android-x86/kernel.git] / drivers / staging / rtl8723bs / include / HalPwrSeqCmd.h

diff --git a/drivers/staging/rtl8723bs/include/HalPwrSeqCmd.h b/drivers/staging/rtl8723bs/include/HalPwrSeqCmd.h
index e5d151c..5bb9f5a 100644 (file)
--- a/drivers/staging/rtl8723bs/include/HalPwrSeqCmd.h
+++ b/drivers/staging/rtl8723bs/include/HalPwrSeqCmd.h
@@ -11,11 +11,6 @@
  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  * more details.
  *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
  ******************************************************************************/
 #ifndef __HALPWRSEQCMD_H__
 #define __HALPWRSEQCMD_H__
@@ -23,51 +18,51 @@
 #include <drv_types.h>
 
 /*---------------------------------------------*/
-//3 The value of cmd: 4 bits
+/* 3 The value of cmd: 4 bits */
 /*---------------------------------------------*/
 #define PWR_CMD_READ                   0x00
-     // offset: the read register offset
-     // msk: the mask of the read value
-     // value: N/A, left by 0
-     // note: dirver shall implement this function by read & msk
+     /*  offset: the read register offset */
+     /*  msk: the mask of the read value */
+     /*  value: N/A, left by 0 */
+     /*  note: dirver shall implement this function by read & msk */
 
 #define PWR_CMD_WRITE                  0x01
-     // offset: the read register offset
-     // msk: the mask of the write bits
-     // value: write value
-     // note: driver shall implement this cmd by read & msk after write
+     /*  offset: the read register offset */
+     /*  msk: the mask of the write bits */
+     /*  value: write value */
+     /*  note: driver shall implement this cmd by read & msk after write */
 
 #define PWR_CMD_POLLING                        0x02
-     // offset: the read register offset
-     // msk: the mask of the polled value
-     // value: the value to be polled, masked by the msd field.
-     // note: driver shall implement this cmd by
-     // do{
-     // if( (Read(offset) & msk) == (value & msk) )
-     // break;
-     // } while(not timeout);
+     /*  offset: the read register offset */
+     /*  msk: the mask of the polled value */
+     /*  value: the value to be polled, masked by the msd field. */
+     /*  note: driver shall implement this cmd by */
+     /*  do{ */
+     /*  if ((Read(offset) & msk) == (value & msk)) */
+     /*  break; */
+     /*  } while (not timeout); */
 
 #define PWR_CMD_DELAY                  0x03
-     // offset: the value to delay
-     // msk: N/A
-     // value: the unit of delay, 0: us, 1: ms
+     /*  offset: the value to delay */
+     /*  msk: N/A */
+     /*  value: the unit of delay, 0: us, 1: ms */
 
 #define PWR_CMD_END                            0x04
-     // offset: N/A
-     // msk: N/A
-     // value: N/A
+     /*  offset: N/A */
+     /*  msk: N/A */
+     /*  value: N/A */
 
 /*---------------------------------------------*/
-//3 The value of base: 4 bits
+/* 3 The value of base: 4 bits */
 /*---------------------------------------------*/
-   // define the base address of each block
+   /*  define the base address of each block */
 #define PWR_BASEADDR_MAC               0x00
 #define PWR_BASEADDR_USB               0x01
 #define PWR_BASEADDR_PCIE              0x02
 #define PWR_BASEADDR_SDIO              0x03
 
 /*---------------------------------------------*/
-//3 The value of interface_msk: 4 bits
+/* 3 The value of interface_msk: 4 bits */
 /*---------------------------------------------*/
 #define        PWR_INTF_SDIO_MSK               BIT(0)
 #define        PWR_INTF_USB_MSK                BIT(1)
@@ -75,14 +70,14 @@
 #define        PWR_INTF_ALL_MSK                (BIT(0)|BIT(1)|BIT(2)|BIT(3))
 
 /*---------------------------------------------*/
-//3 The value of fab_msk: 4 bits
+/* 3 The value of fab_msk: 4 bits */
 /*---------------------------------------------*/
 #define        PWR_FAB_TSMC_MSK                BIT(0)
 #define        PWR_FAB_UMC_MSK                 BIT(1)
 #define        PWR_FAB_ALL_MSK                 (BIT(0)|BIT(1)|BIT(2)|BIT(3))
 
 /*---------------------------------------------*/
-//3 The value of cut_msk: 8 bits
+/* 3 The value of cut_msk: 8 bits */
 /*---------------------------------------------*/
 #define        PWR_CUT_TESTCHIP_MSK    BIT(0)
 #define        PWR_CUT_A_MSK                   BIT(1)
@@ -124,14 +119,14 @@ typedef struct _WL_PWR_CFG_
 #define GET_PWR_CFG_VALUE(__PWR_CMD)           __PWR_CMD.value
 
 
-//================================================================================
-//     Prototype of protected function.
-//================================================================================
+/*  */
+/*     Prototype of protected function. */
+/*  */
 u8 HalPwrSeqCmdParsing(
-       PADAPTER                padapter,
-       u8                              CutVersion,
-       u8                              FabVersion,
-       u8                              InterfaceType,
+       struct adapter *        padapter,
+       u8              CutVersion,
+       u8              FabVersion,
+       u8              InterfaceType,
        WLAN_PWR_CFG    PwrCfgCmd[]);
 
 #endif