--- /dev/null
+\r
+#include "core.h"\r
+\r
+#define PORT_PCI_CONFIG_ADDRESS 0x0cf8 //32bit R/W\r
+#define PORT_PCI_CONFIG_DATA_BASE 0x0cfc //4ports anysize R/W\r
+\r
+typedef union PCI_CONFIG_ADDRESS_REGISTER {\r
+ uint reg;\r
+ struct PCI_CONFIG_ADDRESS_REGISTER_BIT {\r
+ unsigned reserved0 : 2; //0\r
+ unsigned register_num : 6;\r
+ unsigned function_num : 3;\r
+ unsigned device_num : 5;\r
+ unsigned bus_num : 8;\r
+ unsigned reserved1 : 7; //0\r
+ unsigned enable : 1; //PCI_CDRn\82É\83A\83N\83Z\83X\82·\82é\82Æ\82«\82É1\82É\82·\82é\81B\r
+ } bit;\r
+} PCI_ConfigurationAddressRegister;\r
+\r
+//\91S\83f\83o\83C\83X\8b¤\92Ê\82Ì\83R\83\93\83t\83B\83M\83\85\83\8c\81[\83V\83\87\83\93\83\8c\83W\83X\83^:\r
+//0x00:00-15:\83x\83\93\83_ID(ReadOnly)\r
+//0x00:16-31:\83f\83o\83C\83XID(ReadOnly)\r
+//0x04:00-15:\83R\83}\83\93\83h\83\8c\83W\83X\83^(R/W)\r
+// 00:I/O\8bó\8aÔ\83C\83l\81[\83u\83\8b\r
+// 01:\83\81\83\82\83\8a\8bó\8aÔ\83C\83l\81[\83u\83\8b\r
+// 02:\83o\83X\83}\83X\83^\81[\r
+// 03:\83X\83y\83V\83\83\83\8b\83T\83C\83N\83\8b\r
+// 04:\83\81\83\82\83\8a\83\89\83C\83g\81E\83C\83\93\83o\83\8a\83f\81[\83g\83C\83l\81[\83u\83\8b\r
+// 05:VGA\83p\83\8c\83b\83g\83X\83k\81[\83v\r
+// 06:\83p\83\8a\83e\83B\83G\83\89\81[\89\9e\93\9a(0\82Å\95ñ\8d\90\82È\82µ)\r
+// 07:\83E\83F\83C\83g\83T\83C\83N\83\8b\90§\8cä\r
+// 08:SERR#\83C\83l\81[\83u\83\8b\r
+// 09:\8d\82\91¬\83o\83b\83N\83c\81[\83o\83b\83N\83C\83l\81[\83u\83\8b\r
+// 10-15:\83\8a\83U\81[\83u\r
+//0x04:16-31:\83X\83e\81[\83^\83X\83\8c\83W\83X\83^(R/W Write\8e\9eTrue\82Ì\83r\83b\83g\82ª\83N\83\8a\83A\82³\82ê\82é)\r
+// 16-20:\83\8a\83U\81[\83u\r
+// 21:66MHz\91Î\89\9e\89Â\94\\r
+// 22:\83\86\81[\83U\81[\92è\8b`\8b@\94\\82 \82è\r
+// 23:\8d\82\91¬\83o\83b\83N\83c\81[\83o\83b\83N\89Â\94\\r
+// 24:\83f\81[\83^\83p\83\8a\83e\83B\83G\83\89\81[\8c\9f\92m(\83o\83X\83}\83X\83^\81[\8e\9e\82Ì\83G\83\89\81[)\r
+// 25-26:DEVSEL#\83^\83C\83~\83\93\83O(0:\8d\82\91¬ 1:\92\86\91¬ 2:\92á\91¬ 3:\97\\96ñ)\r
+// 27:\83^\81[\83Q\83b\83g\83A\83{\81[\83g\92Ê\92m\r
+// 28:\83^\81[\83Q\83b\83g\83A\83{\81[\83g\8eó\90M\r
+// 29:\83}\83X\83^\81[\83A\83{\81[\83g\8eó\90M\r
+// 30:\83V\83X\83e\83\80\83G\83\89\81[\92Ê\92m\r
+// 31:\83p\83\8a\83e\83B\83G\83\89\81[\8c\9f\92m\r
+//0x08:00-07:\83\8a\83r\83W\83\87\83\93ID(ReadOnly)\r
+//0x08:08-31:\83N\83\89\83X\83R\81[\83h(ReadOnly)\r
+// 08-15:\83v\83\8d\83O\83\89\83\80\83C\83\93\83^\81[\83t\83F\81[\83X\r
+// 16-23:\83T\83u\83N\83\89\83X\r
+// 24-31:\83x\81[\83X\83N\83\89\83X\r
+//0x0c:00-07:\83L\83\83\83b\83V\83\85\83\89\83C\83\93\83T\83C\83Y\r
+//0x0c:08-15:\83}\83X\83^\83\8c\83C\83e\83\93\83V\83^\83C\83}\r
+//0x0c:16-23:\83w\83b\83_\83^\83C\83v(ReadOnly)\r
+// 16-22:\83f\83o\83C\83X\83^\83C\83v(0:\92Ê\8fí\82ÌPCI\83f\83o\83C\83X 1:PCI-PCI\83u\83\8a\83b\83W 2:CardBus\83u\83\8a\83b\83W)\r
+// 23:\83}\83\8b\83`\83t\83@\83\93\83N\83V\83\87\83\93\83f\83o\83C\83X\r
+//0x0c:24-31:BIST\83\8c\83W\83X\83^\r
+\r
+typedef struct PCI_DEVICE_VENDOR {\r
+ uint id;\r
+ uchar *name;\r
+} PCI_Device_VendorID;\r
+\r
+typedef struct PCI_DEVICE_CLASS {\r
+ uint id;\r
+ uchar *name;\r
+} PCI_Device_Class;\r
+\r
+typedef struct PCI_DEVICE_TYPE {\r
+ uint id;\r
+ uchar *name;\r
+} PCI_Device_Type;\r
+\r
+PCI_Device_VendorID pci_device_vendor[] = {\r
+ {0x10ec, "Realtek Semiconductor Corp."},\r
+ {0x8086, "Intel"},\r
+ {0xffff, "[Unknown]"},\r
+// {0x, ""},\r
+};\r
+\r
+PCI_Device_Class pci_device_class[] = {\r
+ {0x010100, "Ultra ATA storage controller"},\r
+ {0x010180, "bus master IDE controller (UDMA33?)"},\r
+ {0x020000, "ethernet adapter ?"},\r
+ {0x030000, "VGA compatible controller"},\r
+ {0x040100, "audio device"},\r
+ {0x060000, "CPU to PCI bridge"},\r
+ {0x060100, "PCI to ISA bridge"},\r
+ {0x068000, "power management controller"},\r
+ {0xff0000, "[Unknown]"},\r
+};\r
+\r
+PCI_Device_Type pci_device_type[] = {\r
+ {0, "Standard PCI Device"},\r
+ {1, "PCI-PCI Bridge"},\r
+ {2, "CardBus Bridge"},\r
+ {3, "[Undefined]"},\r
+};\r
+\r
+void Initialize_PCI(void)\r
+{\r
+ #ifdef CHNOSPROJECT_DEBUG_PCI\r
+ uint data, bus, device, function;\r
+ #endif\r
+\r
+//PCICAR\8f\89\8aú\89»\r
+ IO_Out32(PORT_PCI_CONFIG_ADDRESS, 0x00000000);\r
+\r
+ #ifdef CHNOSPROJECT_DEBUG_PCI\r
+ for(bus = 0; bus < 256; bus++){\r
+ for(device = 0; device < 32; device++){\r
+ for(function = 0; function < 8; function++){\r
+ PCI_ConfigurationRegister_SelectDevice(bus, device, function);\r
+ data = PCI_ConfigurationRegister_Read32(0x00);\r
+ if(data != 0xffffffff){\r
+ debug("PCI:Bus%d.Device%d.Function%d:\n", bus, device, function);\r
+ debug("PCI: DeviceVendor:%s(0x%04X)\n", PCI_GetDeviceVendor(data & 0xffff), data & 0xffff);\r
+\r
+ debug("PCI: DeviceID:0x%04X\n", data >> 16);\r
+\r
+ data = PCI_ConfigurationRegister_Read32(0x08);\r
+ data = CFunction_ExtractBits(data, 8, 31);\r
+ debug("PCI: ClassCode:%s(0x%06X)\n", PCI_GetDeviceClass(data), data);\r
+\r
+ data = PCI_ConfigurationRegister_Read32(0x0c);\r
+ data = CFunction_ExtractBits(data, 16, 22);\r
+ debug("PCI: DeviceType:%s(%d)\n", PCI_GetDeviceType(data), data);\r
+ }\r
+ }\r
+ }\r
+ }\r
+ #endif\r
+\r
+ return;\r
+}\r
+\r
+void PCI_ConfigurationRegister_SelectDevice(uint bus, uint device, uint function)\r
+{\r
+ PCI_ConfigurationAddressRegister pcicar;\r
+ pcicar.reg = IO_In32(PORT_PCI_CONFIG_ADDRESS);\r
+ pcicar.bit.bus_num = bus;\r
+ pcicar.bit.device_num = device;\r
+ pcicar.bit.function_num = function;\r
+ IO_Out32(PORT_PCI_CONFIG_ADDRESS, pcicar.reg);\r
+\r
+ return;\r
+}\r
+\r
+uint PCI_ConfigurationRegister_Read32(uint addr)\r
+{\r
+ PCI_ConfigurationAddressRegister pcicar;\r
+ uint data;\r
+\r
+ pcicar.reg = IO_In32(PORT_PCI_CONFIG_ADDRESS);\r
+ pcicar.bit.register_num = addr >> 2;\r
+ pcicar.bit.enable = True;\r
+ IO_Out32(PORT_PCI_CONFIG_ADDRESS, pcicar.reg);\r
+ data = IO_In32(PORT_PCI_CONFIG_DATA_BASE + (addr & 0x03));\r
+ pcicar.bit.enable = False;\r
+ IO_Out32(PORT_PCI_CONFIG_ADDRESS, pcicar.reg);\r
+\r
+ return data;\r
+}\r
+\r
+uchar *PCI_GetDeviceVendor(uint id)\r
+{\r
+ uint i;\r
+\r
+ for(i = 0; pci_device_vendor[i].id != 0xffff; i++){\r
+ if(pci_device_vendor[i].id == id){\r
+ break;\r
+ }\r
+ }\r
+\r
+ return pci_device_vendor[i].name;\r
+}\r
+\r
+uchar *PCI_GetDeviceClass(uint id)\r
+{\r
+ uint i;\r
+\r
+ for(i = 0; pci_device_class[i].id != 0xff0000; i++){\r
+ if(pci_device_class[i].id == id){\r
+ break;\r
+ }\r
+ }\r
+\r
+ return pci_device_class[i].name;\r
+}\r
+\r
+uchar *PCI_GetDeviceType(uint id)\r
+{\r
+ uint i;\r
+\r
+ for(i = 0; pci_device_type[i].id != 3; i++){\r
+ if(pci_device_type[i].id == id){\r
+ break;\r
+ }\r
+ }\r
+\r
+ return pci_device_type[i].name;\r
+}\r
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