-/*\r
- TOSHIBA PASOPIA 7 Emulator 'EmuPIA7'\r
-\r
- Author : Takeda.Toshiya\r
- Date : 2006.09.20 -\r
-\r
- [ memory ]\r
-*/\r
-\r
-#include "memory.h"\r
-#include "iobus.h"\r
-#include "../i8255.h"\r
-#include "../../fileio.h"\r
-\r
-#define SET_BANK(s, e, w, r) { \\r
- int sb = (s) >> 12, eb = (e) >> 12; \\r
- for(int i = sb; i <= eb; i++) { \\r
- if((w) == wdmy) { \\r
- wbank[i] = wdmy; \\r
- } else { \\r
- wbank[i] = (w) + 0x1000 * (i - sb); \\r
- } \\r
- if((r) == rdmy) { \\r
- rbank[i] = rdmy; \\r
- } else { \\r
- rbank[i] = (r) + 0x1000 * (i - sb); \\r
- } \\r
- } \\r
-}\r
-\r
-void MEMORY::initialize()\r
-{\r
- memset(bios, 0xff, sizeof(bios));\r
- memset(basic, 0xff, sizeof(basic));\r
- memset(rdmy, 0xff, sizeof(rdmy));\r
- \r
- // load rom images\r
- FILEIO* fio = new FILEIO();\r
- if(fio->Fopen(emu->bios_path(_T("BIOS.ROM")), FILEIO_READ_BINARY)) {\r
- fio->Fread(bios, sizeof(bios), 1);\r
- fio->Fclose();\r
- }\r
- if(fio->Fopen(emu->bios_path(_T("BASIC.ROM")), FILEIO_READ_BINARY)) {\r
- fio->Fread(basic, sizeof(basic), 1);\r
- fio->Fclose();\r
- }\r
- delete fio;\r
- \r
- mem_map = 0xff;\r
- update_memory_map();\r
- \r
- plane = 0;\r
- vram_sel = pal_sel = attr_wrap = false;\r
-}\r
-\r
-void MEMORY::reset()\r
-{\r
- memset(vram, 0, sizeof(vram));\r
-}\r
-\r
-void MEMORY::write_data8(uint32 addr, uint32 data)\r
-{\r
- addr &= 0xffff;\r
- if(vram_sel && (addr & 0xc000) == 0x8000) {\r
- if(pal_sel && !(plane & 0x70)) {\r
- pal[addr & 0x0f] = data & 0x0f;\r
- return;\r
- }\r
- uint32 laddr = addr & 0x3fff;\r
- if(plane & 0x10) {\r
- vram[0x0000 | laddr] = (plane & 0x1) ? data : 0xff;\r
- }\r
- if(plane & 0x20) {\r
- vram[0x4000 | laddr] = (plane & 0x2) ? data : 0xff;\r
- }\r
- if(plane & 0x40) {\r
- vram[0x8000 | laddr] = (plane & 0x4) ? data : 0xff;\r
- attr_latch = attr_wrap ? attr_latch : attr_data;\r
- vram[0xc000 | laddr] = attr_latch;\r
- // 8255-0, Port B\r
- d_pio0->write_signal(SIG_I8255_PORT_B, (attr_latch << 4) | (attr_latch & 7), 0x87);\r
- }\r
- return;\r
- }\r
- wbank[addr >> 12][addr & 0xfff] = data;\r
-}\r
-\r
-uint32 MEMORY::read_data8(uint32 addr)\r
-{\r
- addr &= 0xffff;\r
- if(vram_sel && (addr & 0xc000) == 0x8000) {\r
- if(pal_sel && !(plane & 0x70)) {\r
- return pal[addr & 0x0f];\r
- }\r
- uint32 laddr = addr & 0x3fff, val = 0xff;\r
- if((plane & 0x11) == 0x11) {\r
- val &= vram[0x0000 | laddr];\r
- }\r
- if((plane & 0x22) == 0x22) {\r
- val &= vram[0x4000 | laddr];\r
- }\r
- if((plane & 0x44) == 0x44) {\r
- attr_latch = vram[0xc000 | laddr];\r
- val &= vram[0x8000 | laddr];\r
- // 8255-0, Port B\r
- d_pio0->write_signal(SIG_I8255_PORT_B, (attr_latch << 4) | (attr_latch & 7), 0x87);\r
- }\r
- return val;\r
- }\r
- return rbank[addr >> 12][addr & 0xfff];\r
-}\r
-\r
-void MEMORY::write_io8(uint32 addr, uint32 data)\r
-{\r
- if(mem_map != (data & 7)) {\r
- mem_map = data & 7;\r
- update_memory_map();\r
- }\r
- vram_sel = ((data & 4) != 0);\r
- \r
- // I/O memory access\r
- d_iobus->write_signal(SIG_IOBUS_MIO, data, 8);\r
- \r
- // 8255-2, Port C\r
- d_pio2->write_signal(SIG_I8255_PORT_C, data, 3);\r
-}\r
-\r
-void MEMORY::write_signal(int id, uint32 data, uint32 mask)\r
-{\r
- if(id == SIG_MEMORY_I8255_1_A) {\r
- plane = data;\r
- } else if(id == SIG_MEMORY_I8255_1_B) {\r
- attr_data = data & 0x0f;\r
- } else if(id == SIG_MEMORY_I8255_1_C) {\r
- attr_wrap = ((data & 0x10) != 0);\r
- pal_sel = ((data & 0x0c) != 0);\r
- }\r
-}\r
-\r
-void MEMORY::update_memory_map()\r
-{\r
- if(mem_map == 0xff) {\r
- SET_BANK(0x0000, 0x3fff, wdmy, bios);\r
- SET_BANK(0x4000, 0x7fff, wdmy, bios);\r
- SET_BANK(0x8000, 0xbfff, wdmy, bios);\r
- SET_BANK(0xc000, 0xffff, wdmy, bios);\r
- } else {\r
- if(mem_map & 2) {\r
- SET_BANK(0x0000, 0x3fff, ram + 0x0000, ram + 0x0000);\r
- } else {\r
- SET_BANK(0x0000, 0x3fff, ram + 0x0000, basic + 0x0000);\r
- }\r
- if(mem_map & 1) {\r
- SET_BANK(0x4000, 0x7fff, ram + 0x4000, bios + 0x0000);\r
- } else if(mem_map & 2) {\r
- SET_BANK(0x4000, 0x7fff, ram + 0x4000, ram + 0x4000);\r
- } else {\r
- SET_BANK(0x4000, 0x7fff, ram + 0x4000, basic + 0x4000);\r
- }\r
- if(mem_map & 4) {\r
- SET_BANK(0x8000, 0xbfff, wdmy, rdmy);\r
- } else {\r
- SET_BANK(0x8000, 0xbfff, ram + 0x8000, ram + 0x8000);\r
- }\r
- SET_BANK(0xc000, 0xffff, ram + 0xc000, ram + 0xc000);\r
- }\r
-}\r
-\r
-#define STATE_VERSION 1\r
-\r
-void MEMORY::save_state(FILEIO* state_fio)\r
-{\r
- state_fio->FputUint32(STATE_VERSION);\r
- state_fio->FputInt32(this_device_id);\r
- \r
- state_fio->Fwrite(ram, sizeof(ram), 1);\r
- state_fio->Fwrite(vram, sizeof(vram), 1);\r
- state_fio->Fwrite(pal, sizeof(pal), 1);\r
- state_fio->FputUint8(mem_map);\r
- state_fio->FputUint8(plane);\r
- state_fio->FputUint8(attr_data);\r
- state_fio->FputUint8(attr_latch);\r
- state_fio->FputBool(vram_sel);\r
- state_fio->FputBool(pal_sel);\r
- state_fio->FputBool(attr_wrap);\r
-}\r
-\r
-bool MEMORY::load_state(FILEIO* state_fio)\r
-{\r
- if(state_fio->FgetUint32() != STATE_VERSION) {\r
- return false;\r
- }\r
- if(state_fio->FgetInt32() != this_device_id) {\r
- return false;\r
- }\r
- state_fio->Fread(ram, sizeof(ram), 1);\r
- state_fio->Fread(vram, sizeof(vram), 1);\r
- state_fio->Fread(pal, sizeof(pal), 1);\r
- mem_map = state_fio->FgetUint8();\r
- plane = state_fio->FgetUint8();\r
- attr_data = state_fio->FgetUint8();\r
- attr_latch = state_fio->FgetUint8();\r
- vram_sel = state_fio->FgetBool();\r
- pal_sel = state_fio->FgetBool();\r
- attr_wrap = state_fio->FgetBool();\r
- \r
- // post process\r
- update_memory_map();\r
- return true;\r
-}\r
-\r
+/*
+ TOSHIBA PASOPIA 7 Emulator 'EmuPIA7'
+
+ Author : Takeda.Toshiya
+ Date : 2006.09.20 -
+
+ [ memory ]
+*/
+
+#include "./memory.h"
+#include "iobus.h"
+#include "../i8255.h"
+
+#define SET_BANK(s, e, w, r) { \
+ int sb = (s) >> 12, eb = (e) >> 12; \
+ for(int i = sb; i <= eb; i++) { \
+ if((w) == wdmy) { \
+ wbank[i] = wdmy; \
+ } else { \
+ wbank[i] = (w) + 0x1000 * (i - sb); \
+ } \
+ if((r) == rdmy) { \
+ rbank[i] = rdmy; \
+ } else { \
+ rbank[i] = (r) + 0x1000 * (i - sb); \
+ } \
+ } \
+}
+
+void PASOPIA7_MEMORY::initialize()
+{
+ memset(bios, 0xff, sizeof(bios));
+ memset(basic, 0xff, sizeof(basic));
+ memset(rdmy, 0xff, sizeof(rdmy));
+
+ // load rom images
+ FILEIO* fio = new FILEIO();
+ if(fio->Fopen(create_local_path(_T("BIOS.ROM")), FILEIO_READ_BINARY)) {
+ fio->Fread(bios, sizeof(bios), 1);
+ fio->Fclose();
+ }
+ if(fio->Fopen(create_local_path(_T("BASIC.ROM")), FILEIO_READ_BINARY)) {
+ fio->Fread(basic, sizeof(basic), 1);
+ fio->Fclose();
+ }
+ delete fio;
+
+ mem_map = 0xff;
+ update_memory_map();
+
+ plane = 0;
+ vram_sel = pal_sel = attr_wrap = false;
+}
+
+void PASOPIA7_MEMORY::reset()
+{
+ memset(vram, 0, sizeof(vram));
+}
+
+void PASOPIA7_MEMORY::write_data8(uint32_t addr, uint32_t data)
+{
+ addr &= 0xffff;
+ if(vram_sel && (addr & 0xc000) == 0x8000) {
+ if(pal_sel && !(plane & 0x70)) {
+ pal[addr & 0x0f] = data & 0x0f;
+ return;
+ }
+ uint32_t laddr = addr & 0x3fff;
+ if(plane & 0x10) {
+ vram[0x0000 | laddr] = (plane & 0x1) ? data : 0xff;
+ }
+ if(plane & 0x20) {
+ vram[0x4000 | laddr] = (plane & 0x2) ? data : 0xff;
+ }
+ if(plane & 0x40) {
+ vram[0x8000 | laddr] = (plane & 0x4) ? data : 0xff;
+ attr_latch = attr_wrap ? attr_latch : attr_data;
+ vram[0xc000 | laddr] = attr_latch;
+ // 8255-0, Port B
+ d_pio0->write_signal(SIG_I8255_PORT_B, (attr_latch << 4) | (attr_latch & 7), 0x87);
+ }
+ return;
+ }
+ wbank[addr >> 12][addr & 0xfff] = data;
+}
+
+uint32_t PASOPIA7_MEMORY::read_data8(uint32_t addr)
+{
+ addr &= 0xffff;
+ if(vram_sel && (addr & 0xc000) == 0x8000) {
+ if(pal_sel && !(plane & 0x70)) {
+ return pal[addr & 0x0f];
+ }
+ uint32_t laddr = addr & 0x3fff, val = 0xff;
+ if((plane & 0x11) == 0x11) {
+ val &= vram[0x0000 | laddr];
+ }
+ if((plane & 0x22) == 0x22) {
+ val &= vram[0x4000 | laddr];
+ }
+ if((plane & 0x44) == 0x44) {
+ attr_latch = vram[0xc000 | laddr];
+ val &= vram[0x8000 | laddr];
+ // 8255-0, Port B
+ d_pio0->write_signal(SIG_I8255_PORT_B, (attr_latch << 4) | (attr_latch & 7), 0x87);
+ }
+ return val;
+ }
+ return rbank[addr >> 12][addr & 0xfff];
+}
+
+void PASOPIA7_MEMORY::write_io8(uint32_t addr, uint32_t data)
+{
+ if(mem_map != (data & 7)) {
+ mem_map = data & 7;
+ update_memory_map();
+ }
+ vram_sel = ((data & 4) != 0);
+
+ // I/O memory access
+ d_iobus->write_signal(SIG_IOBUS_MIO, data, 8);
+
+ // 8255-2, Port C
+ d_pio2->write_signal(SIG_I8255_PORT_C, data, 3);
+}
+
+void PASOPIA7_MEMORY::write_signal(int id, uint32_t data, uint32_t mask)
+{
+ if(id == SIG_MEMORY_I8255_1_A) {
+ plane = data;
+ } else if(id == SIG_MEMORY_I8255_1_B) {
+ attr_data = data & 0x0f;
+ } else if(id == SIG_MEMORY_I8255_1_C) {
+ attr_wrap = ((data & 0x10) != 0);
+ pal_sel = ((data & 0x0c) != 0);
+ }
+}
+
+void PASOPIA7_MEMORY::update_memory_map()
+{
+ if(mem_map == 0xff) {
+ SET_BANK(0x0000, 0x3fff, wdmy, bios);
+ SET_BANK(0x4000, 0x7fff, wdmy, bios);
+ SET_BANK(0x8000, 0xbfff, wdmy, bios);
+ SET_BANK(0xc000, 0xffff, wdmy, bios);
+ } else {
+ if(mem_map & 2) {
+ SET_BANK(0x0000, 0x3fff, ram + 0x0000, ram + 0x0000);
+ } else {
+ SET_BANK(0x0000, 0x3fff, ram + 0x0000, basic + 0x0000);
+ }
+ if(mem_map & 1) {
+ SET_BANK(0x4000, 0x7fff, ram + 0x4000, bios + 0x0000);
+ } else if(mem_map & 2) {
+ SET_BANK(0x4000, 0x7fff, ram + 0x4000, ram + 0x4000);
+ } else {
+ SET_BANK(0x4000, 0x7fff, ram + 0x4000, basic + 0x4000);
+ }
+ if(mem_map & 4) {
+ SET_BANK(0x8000, 0xbfff, wdmy, rdmy);
+ } else {
+ SET_BANK(0x8000, 0xbfff, ram + 0x8000, ram + 0x8000);
+ }
+ SET_BANK(0xc000, 0xffff, ram + 0xc000, ram + 0xc000);
+ }
+}
+
+#define STATE_VERSION 1
+
+bool PASOPIA7_MEMORY::process_state(FILEIO* state_fio, bool loading)
+{
+ if(!state_fio->StateCheckUint32(STATE_VERSION)) {
+ return false;
+ }
+ if(!state_fio->StateCheckInt32(this_device_id)) {
+ return false;
+ }
+ state_fio->StateBuffer(ram, sizeof(ram), 1);
+ state_fio->StateBuffer(vram, sizeof(vram), 1);
+ state_fio->StateBuffer(pal, sizeof(pal), 1);
+ state_fio->StateUint8(mem_map);
+ state_fio->StateUint8(plane);
+ state_fio->StateUint8(attr_data);
+ state_fio->StateUint8(attr_latch);
+ state_fio->StateBool(vram_sel);
+ state_fio->StateBool(pal_sel);
+ state_fio->StateBool(attr_wrap);
+
+ // post process
+ if(loading) {
+ update_memory_map();
+ }
+ return true;
+}
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