; ----------------------------------------------------------------------
; PC = P6:P5
-PCIN .set PC_SFR + 00h ; Port C Input
-PCOUT .set PC_SFR + 02h ; Port C Output 1/0 or pullup/pulldown resistor
-PCDIR .set PC_SFR + 04h ; Port C Direction
-PCREN .set PC_SFR + 06h ; Port C Resistor Enable
-PCSEL0 .set PC_SFR + 0Ah ; Port C Selection 0
-PCSEL1 .set PC_SFR + 0Ch ; Port C Selection 1
+PCIN .equ PC_SFR + 00h ; Port C Input
+PCOUT .equ PC_SFR + 02h ; Port C Output 1/0 or pullup/pulldown resistor
+PCDIR .equ PC_SFR + 04h ; Port C Direction
+PCREN .equ PC_SFR + 06h ; Port C Resistor Enable
+PCSEL0 .equ PC_SFR + 0Ah ; Port C Selection 0
+PCSEL1 .equ PC_SFR + 0Ch ; Port C Selection 1
-P5IN .set PC_SFR + 00h ; Port 5 Input */
-P5OUT .set PC_SFR + 02h ; Port 5 Output
-P5DIR .set PC_SFR + 04h ; Port 5 Direction
-P5REN .set PC_SFR + 06h ; Port 5 Resistor Enable
-P5SEL0 .set PC_SFR + 0Ah ; Port 5 Selection 0
-P5SEL1 .set PC_SFR + 0Ch ; Port 5 Selection 1
+P5IN .equ PC_SFR + 00h ; Port 5 Input */
+P5OUT .equ PC_SFR + 02h ; Port 5 Output
+P5DIR .equ PC_SFR + 04h ; Port 5 Direction
+P5REN .equ PC_SFR + 06h ; Port 5 Resistor Enable
+P5SEL0 .equ PC_SFR + 0Ah ; Port 5 Selection 0
+P5SEL1 .equ PC_SFR + 0Ch ; Port 5 Selection 1
-P6IN .set PC_SFR + 01h ; Port 6 Input */
-P6OUT .set PC_SFR + 03h ; Port 6 Output
-P6DIR .set PC_SFR + 05h ; Port 6 Direction
-P6REN .set PC_SFR + 07h ; Port 6 Resistor Enable
-P6SEL0 .set PC_SFR + 0Bh ; Port 6 Selection 0
-P6SEL1 .set PC_SFR + 0Dh ; Port 6 Selection 1
+P6IN .equ PC_SFR + 01h ; Port 6 Input */
+P6OUT .equ PC_SFR + 03h ; Port 6 Output
+P6DIR .equ PC_SFR + 05h ; Port 6 Direction
+P6REN .equ PC_SFR + 07h ; Port 6 Resistor Enable
+P6SEL0 .equ PC_SFR + 0Bh ; Port 6 Selection 0
+P6SEL1 .equ PC_SFR + 0Dh ; Port 6 Selection 1
MPY32CTL0 .equ MPY_SFR + 2Ch ; MPY32 control register 0
-; ----------------------------------------------------------------------
-eUSCI_A0
-; ----------------------------------------------------------------------
-
- .IFDEF UCA0_TERM
-TERM_CTLW0 .equ eUSCI_A0_SFR + 00h ; eUSCI_A0 Control Word Register 0
-TERM_BRW .equ eUSCI_A0_SFR + 06h ; eUSCI_A0 Baud Word Rate 0
-TERM_MCTLW .equ eUSCI_A0_SFR + 08h ; eUSCI_A0 Modulation Control
-TERM_STATW .equ eUSCI_A0_SFR + 0Ah ; eUSCI_A0 status Word Register
-TERM_RXBUF .equ eUSCI_A0_SFR + 0Ch ; eUSCI_A0 Receive Buffer
-TERM_TXBUF .equ eUSCI_A0_SFR + 0Eh ; eUSCI_A0 Transmit Buffer
-TERM_IE .equ eUSCI_A0_SFR + 1Ah ; eUSCI_A0 Interrupt Enable Register
-TERM_IFG .equ eUSCI_A0_SFR + 1Ch ; eUSCI_A0 Interrupt Flags Register
-TERM_VEC .equ 0FFE4h ; int vector for eUSCI_A0
-RX_TERM .equ 1
-TX_TERM .equ 2
- .ENDIF ;UCA0_TERM
-
- .IFDEF UCA0_SD
-SD_CTLW0 .equ eUSCI_A0_SFR + 00h ; eUSCI_A0 Control Word Register 0
-SD_BRW .equ eUSCI_A0_SFR + 06h ; eUSCI_A0 Baud Word Rate 0
-SD_RXBUF .equ eUSCI_A0_SFR + 0Ch ; eUSCI_A0 Receive Buffer 8
-SD_TXBUF .equ eUSCI_A0_SFR + 0Eh ; eUSCI_A0 Transmit Buffer 8
-SD_IFG .equ eUSCI_A0_SFR + 1Ch ; eUSCI_A0 Interrupt Flags Register
-RX_SD .equ 1
-TX_SD .equ 2
- .ENDIF ;UCA0_SD
-
-
+ .IFDEF UCA1_TERM
; ----------------------------------------------------------------------
eUSCI_A1
; ----------------------------------------------------------------------
- .IFDEF UCA1_TERM
-TERM_CTLW0 .equ eUSCI_A1_SFR + 00h ; eUSCI_A1 Control Word Register 0
-TERM_BRW .equ eUSCI_A1_SFR + 06h ; eUSCI_A1 Baud Word Rate 0
-TERM_MCTLW .equ eUSCI_A1_SFR + 08h ; eUSCI_A1 Modulation Control
-TERM_STATW .equ eUSCI_A1_SFR + 0Ah ; eUSCI_A1 status Word Register
-TERM_RXBUF .equ eUSCI_A1_SFR + 0Ch ; eUSCI_A1 Receive Buffer
-TERM_TXBUF .equ eUSCI_A1_SFR + 0Eh ; eUSCI_A1 Transmit Buffer
-TERM_IE .equ eUSCI_A1_SFR + 1Ah ; eUSCI_A1 Interrupt Enable Register
-TERM_IFG .equ eUSCI_A1_SFR + 1Ch ; eUSCI_A1 Interrupt Flags Register
-TERM_VEC .equ 0FFE2h ; int vector for eUSCI_A1
+TERM_CTLW0 .equ eUSCI_A1_SFR + 00h ; eUSCI_A1 Control Word Register 0
+TERM_BRW .equ eUSCI_A1_SFR + 06h ; eUSCI_A1 Baud Word Rate 0
+TERM_MCTLW .equ eUSCI_A1_SFR + 08h ; eUSCI_A1 Modulation Control
+TERM_STATW .equ eUSCI_A1_SFR + 0Ah ; eUSCI_A1 status Word Register
+TERM_RXBUF .equ eUSCI_A1_SFR + 0Ch ; eUSCI_A1 Receive Buffer
+TERM_TXBUF .equ eUSCI_A1_SFR + 0Eh ; eUSCI_A1 Transmit Buffer
+TERM_IE .equ eUSCI_A1_SFR + 1Ah ; eUSCI_A1 Interrupt Enable Register
+TERM_IFG .equ eUSCI_A1_SFR + 1Ch ; eUSCI_A1 Interrupt Flags Register
+
+TERM_VEC .equ 0FFE2h ; int vector for eUSCI_A1
+WAKE_UP .equ 1 ; UART RX interrupt
+
RX_TERM .equ 1
TX_TERM .equ 2
.ENDIF ;UCA1_TERM
- .IFDEF UCA1_SD
-SD_CTLW0 .equ eUSCI_A1_SFR + 00h ; eUSCI_A1 Control Word Register 0
-SD_BRW .equ eUSCI_A1_SFR + 06h ; eUSCI_A1 Baud Word Rate 0
-SD_RXBUF .equ eUSCI_A1_SFR + 0Ch ; eUSCI_A1 Receive Buffer 8
-SD_TXBUF .equ eUSCI_A1_SFR + 0Eh ; eUSCI_A1 Transmit Buffer 8
-SD_IFG .equ eUSCI_A1_SFR + 1Ch ; eUSCI_A1 Interrupt Flags Register
-RX_SD .equ 1
-TX_SD .equ 2
- .ENDIF ;UCA1_SD
+ .IFDEF UCB0_TERM
; ----------------------------------------------------------------------
eUSCI_B0
; ----------------------------------------------------------------------
-
- .IFDEF UCB0_TERM
TERM_CTLW0 .equ eUSCI_B0_SFR + 00h ; USCI_B0 Control Word Register 0
TERM_CTLW1 .equ eUSCI_B0_SFR + 02h ; USCI_B0 Control Word Register 1
TERM_BRW .equ eUSCI_B0_SFR + 06h ; USCI_B0 Baud Word Rate 0
TERM_I2CSA .equ eUSCI_B0_SFR + 20h ; USCI_B0 I2C Slave Address
TERM_IE .equ eUSCI_B0_SFR + 2Ah ; USCI_B0 Interrupt Enable
TERM_IFG .equ eUSCI_B0_SFR + 2Ch ; USCI_B0 Interrupt Flags Register
-TERM_VEC .equ 0FFE0h ; interrupt vector for eUSCI_B0
+
+TERM_VEC .equ 0FFE0h ; interrupt vector for eUSCI_B0
+WAKE_UP .equ 4 ; START interrupt
+
RX_TERM .equ 1
TX_TERM .equ 2
.ENDIF ;UCB0_TERM
- .IFDEF UCB0_SD
-SD_CTLW0 .equ eUSCI_B0_SFR + 00h ; USCI_B0 Control Word Register 0
-SD_BRW .equ eUSCI_B0_SFR + 06h ; USCI_B0 Baud Word Rate 0
-SD_RXBUF .equ eUSCI_B0_SFR + 0Ch ; USCI_B0 Receive Buffer 8
-SD_TXBUF .equ eUSCI_B0_SFR + 0Eh ; USCI_B0 Transmit Buffer 8
-SD_IFG .equ eUSCI_B0_SFR + 2Ch ; USCI_B0 Interrupt Flags Register
-RX_SD .equ 1
-TX_SD .equ 2
- .ENDIF ;UCB0_SD
+ .IFDEF UCB1_SD
; ----------------------------------------------------------------------
eUSCI_B1
; ----------------------------------------------------------------------
- .IFDEF UCB1_TERM
-TERM_CTLW0 .equ eUSCI_B1_SFR + 00h ; USCI_B1 Control Word Register 0
-TERM_CTLW1 .equ eUSCI_B1_SFR + 02h ; USCI_B1 Control Word Register 1
-TERM_BRW .equ eUSCI_B1_SFR + 06h ; USCI_B1 Baud Word Rate 0
-TERM_STATW .equ eUSCI_B1_SFR + 08h ; USCI_B1 Status Word
-TERM_RXBUF .equ eUSCI_B1_SFR + 0Ch ; USCI_B1 Receive Buffer 8
-TERM_TXBUF .equ eUSCI_B1_SFR + 0Eh ; USCI_B1 Transmit Buffer 8
-TERM_I2COA0 .equ eUSCI_B1_SFR + 14h ; USCI_B1 I2C Own Address 0
-TERM_ADDRX .equ eUSCI_B1_SFR + 1Ch ; USCI_B1 Received Address Register
-TERM_I2CSA .equ eUSCI_B1_SFR + 20h ; USCI_B1 I2C Slave Address
-TERM_IE .equ eUSCI_B1_SFR + 2Ah ; USCI_B1 Interrupt Enable
-TERM_IFG .equ eUSCI_B1_SFR + 2Ch ; USCI_B1 Interrupt Flags Register
-TERM_VEC .equ 0FFDEh ; interrupt vector for eUSCI_B1
-RX_TERM .equ 1
-TX_TERM .equ 2
- .ENDIF ;UCB1_TERM
-
- .IFDEF UCB1_SD
SD_CTLW0 .equ eUSCI_B1_SFR + 00h ; USCI_B1 Control Word Register 0
SD_BRW .equ eUSCI_B1_SFR + 06h ; USCI_B1 Baud Word Rate 0
SD_RXBUF .equ eUSCI_B1_SFR + 0Ch ; USCI_B1 Receive Buffer 8
SD_TXBUF .equ eUSCI_B1_SFR + 0Eh ; USCI_B1 Transmit Buffer 8
SD_IFG .equ eUSCI_B1_SFR + 2Ch ; USCI_B1 Interrupt Flags Register
+
RX_SD .equ 1
TX_SD .equ 2
.ENDIF ;UCB1_SD