; .org JTAG_PASSWORD ;Start of JTAG PASSWORD
;
; .org INTVECT ; FFCE-FFFF 24 vectors + reset
-; .word reset ; $FFCE - RTC_B
-; .word reset ; $FFD0 - I/O Port 4
-; .word reset ; $FFD2 - I/O Port 3
-; .word reset ; $FFD4 - TB2_1
-; .word reset ; $FFD6 - TB2_0
-; .word reset ; $FFD8 - I/O Port 2
-; .word reset ; $FFDA - TB1_1
-; .word reset ; $FFDC - TB1_0
-; .word reset ; $FFDE - I/O Port 1
+; .word reset ; 0FFCEh - RTC_B
+; .word reset ; 0FFD0h - I/O Port 4
+; .word reset ; 0FFD2h - I/O Port 3
+; .word reset ; 0FFD4h - TB2_1
+; .word reset ; 0FFD6h - TB2_0
+; .word reset ; 0FFD8h - I/O Port 2
+; .word reset ; 0FFDAh - TB1_1
+; .word reset ; 0FFDCh - TB1_0
+; .word reset ; 0FFDEh - I/O Port 1
;; .org BSL_PASSWORD ;Start of BSL PASSWORD
-; .word reset ; $FFE0 - TA1_1
-; .word reset ; $FFE2 - TA1_0
-; .word reset ; $FFE4 - DMA
-; .word reset ; $FFE6 - eUSCI_A1
-; .word reset ; $FFE8 - TA0_1
-; .word reset ; $FFEA - TA0_0
-; .word reset ; $FFEC - ADC10_B
-; .word reset ; $FFEE - eUSCI_B0
-; .word reset ; $FFF0 - eUSCI_A0
-; .word reset ; $FFF2 - Watchdog
-; .word reset ; $FFF4 - TB0_1
-; .word reset ; $FFF6 - TB0_0
-; .word reset ; $FFF8 - COMP_D
-; .word reset ; $FFFA - userNMI
-; .word reset ; $FFFC - sysNMI
-; .word reset ; $FFFE - reset
+; .word reset ; 0FFE0h - TA1_1
+; .word reset ; 0FFE2h - TA1_0
+; .word reset ; 0FFE4h - DMA
+; .word reset ; 0FFE6h - eUSCI_A1
+; .word reset ; 0FFE8h - TA0_1
+; .word reset ; 0FFEAh - TA0_0
+; .word reset ; 0FFECh - ADC10_B
+; .word reset ; 0FFEEh - eUSCI_B0
+; .word reset ; 0FFF0h - eUSCI_A0
+; .word reset ; 0FFF2h - Watchdog
+; .word reset ; 0FFF4h - TB0_1
+; .word reset ; 0FFF6h - TB0_0
+; .word reset ; 0FFF8h - COMP_D
+; .word reset ; 0FFFAh - userNMI
+; .word reset ; 0FFFCh - sysNMI
+; .word reset ; 0FFFEh - reset
; ----------------------------------------------------------------------
; POWER ON RESET AND INITIALIZATION : LOCK I/O as high impedance state
; ----------------------------------------------------------------------
+SFRIE1 .equ SFR_SFR
+SFRIFG1 .equ SFR_SFR + 2
+SFRRPCR .equ SFR_SFR + 4
+
PMMCTL0 .equ PMM_SFR
PMMSWBOR .equ 4
MPUSAM .equ MPU_SFR + 06h ; MPU access management
-UCSWRST .equ 1 ; eUSCI Software Reset
-UCTXIE .equ 2 ; eUSCI Transmit Interrupt Enable
-UCRXIE .equ 1 ; eUSCI Receive Interrupt Enable
-UCTXIFG .equ 2 ; eUSCI Transmit Interrupt Flag
-UCRXIFG .equ 1 ; eUSCI Receive Interrupt Flag
-
-
; ----------------------------------------------------------------------
; eUSCI_A0
; ----------------------------------------------------------------------
TERM_IE .equ eUSCI_A0_SFR + 1Ah ; eUSCI_A0 Interrupt Enable Register
TERM_IFG .equ eUSCI_A0_SFR + 1Ch ; eUSCI_A0 Interrupt Flags Register
TERM_VEC .equ 0FFF0h ; interrupt vector for eUSCI_A0
+RX_TERM .equ 1
+TX_TERM .equ 2
.ENDIF ;UCA0_TERM
; ----------------------------------------------------------------------
; eUSCI_A1
; ----------------------------------------------------------------------
- .IFDEF UCA1_TERM
-TERM_CTLW0 .equ eUSCI_A1_SFR + 00h ; eUSCI_A1 Control Word Register 0
-TERM_BRW .equ eUSCI_A1_SFR + 06h ; eUSCI_A1 Baud Word Rate 0
-TERM_MCTLW .equ eUSCI_A1_SFR + 08h ; eUSCI_A1 Modulation Control
-TERM_STATW .equ eUSCI_A1_SFR + 0Ah ; eUSCI_A1 status Word Register
-TERM_RXBUF .equ eUSCI_A1_SFR + 0Ch ; eUSCI_A1 Receive Buffer
-TERM_TXBUF .equ eUSCI_A1_SFR + 0Eh ; eUSCI_A1 Transmit Buffer
-TERM_IE .equ eUSCI_A1_SFR + 1Ah ; eUSCI_A1 Interrupt Enable Register
-TERM_IFG .equ eUSCI_A1_SFR + 1Ch ; eUSCI_A1 Interrupt Flags Register
- .ENDIF ;UCA1_TERM
+ .IFDEF UCA1_SD
+SD_CTLW0 .equ eUSCI_A1_SFR + 00h ; eUSCI_A1 Control Word Register 0
+SD_BRW .equ eUSCI_A1_SFR + 06h ; eUSCI_A1 Baud Word Rate 0
+SD_RXBUF .equ eUSCI_A1_SFR + 0Ch ; eUSCI_A1 Receive Buffer 8
+SD_TXBUF .equ eUSCI_A1_SFR + 0Eh ; eUSCI_A1 Transmit Buffer 8
+SD_IFG .equ eUSCI_A1_SFR + 1Ch ; eUSCI_A1 Interrupt Flags Register
+RX_SD .equ 1
+TX_SD .equ 2
+ .ENDIF ;UCA1_SD
; ----------------------------------------------------------------------
; eUSCI_B0
; ----------------------------------------------------------------------
- .IFDEF UCB0_SD
-SD_CTLW0 .equ eUSCI_B0_SFR + 00h ; USCI_B0 Control Word Register 0
-SD_BRW .equ eUSCI_B0_SFR + 06h ; USCI_B0 Baud Word Rate 0
-SD_RXBUF .equ eUSCI_B0_SFR + 0Ch ; USCI_B0 Receive Buffer 8
-SD_TXBUF .equ eUSCI_B0_SFR + 0Eh ; USCI_B0 Transmit Buffer 8
-SD_IFG .equ eUSCI_B0_SFR + 2Ch ; USCI_B0 Interrupt Flags Register
- .ENDIF ;UCB0_SD
+ .IFDEF UCB0_TERM
+TERM_CTLW0 .equ eUSCI_B0_SFR + 00h ; USCI_B0 Control Word Register 0
+TERM_CTLW1 .equ eUSCI_B0_SFR + 02h ; USCI_B0 Control Word Register 1
+TERM_BRW .equ eUSCI_B0_SFR + 06h ; USCI_B0 Baud Word Rate 0
+TERM_STATW .equ eUSCI_B0_SFR + 08h ; USCI_B0 Status Word
+TERM_RXBUF .equ eUSCI_B0_SFR + 0Ch ; USCI_B0 Receive Buffer 8
+TERM_TXBUF .equ eUSCI_B0_SFR + 0Eh ; USCI_B0 Transmit Buffer 8
+TERM_I2COA0 .equ eUSCI_B0_SFR + 14h ; USCI_B0 I2C Own Address 0
+TERM_ADDRX .equ eUSCI_B0_SFR + 1Ch ; USCI_B0 Received Address Register
+TERM_I2CSA .equ eUSCI_B0_SFR + 20h ; USCI_B0 I2C Slave Address
+TERM_IE .equ eUSCI_B0_SFR + 2Ah ; USCI_B0 Interrupt Enable
+TERM_IFG .equ eUSCI_B0_SFR + 2Ch ; USCI_B0 Interrupt Flags Register
+TERM_VEC .equ 0FFEEh ; interrupt vector for eUSCI_B0
+RX_TERM .equ 1
+TX_TERM .equ 2
+ .ENDIF ;UCB0_TERM
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