V3.7

[fast-forth/master.git] / inc / MSP_EXP430FR4133.asm

diff --git a/inc/MSP_EXP430FR4133.asm b/inc/MSP_EXP430FR4133.asm
index b05f804..4a2aff5 100644 (file)
--- a/inc/MSP_EXP430FR4133.asm
+++ b/inc/MSP_EXP430FR4133.asm
@@ -288,9 +288,7 @@ CS_SD       .equ 2        ; P8.1
 ; need to adjust FLLN (and DCO) for each device of MSP430fr2xxx family ?
 ; (no problem with MSP430FR5xxx families without FLL).
 ; ===================================================================
-
     .IF FREQUENCY = 0.5
-
 ;            MOV     #058h,&CSCTL0       ; preset DCO = measured value @ 0x180 (88)
 ;            MOV     #0001h,&CSCTL1      ; Set 1MHZ DCORSEL,disable DCOFTRIM,Modulation
             MOV     #1ED1h,&CSCTL0       ; preset MOD=31, DCO = measured value @ 0x180 (209)
@@ -303,10 +301,7 @@ CS_SD       .equ 2        ; P8.1
             MOV     #100Fh,&CSCTL2      ; Set FLLD=1 (DCOCLKCDIV=DCO/2),set FLLN=0Fh
                                         ; fCOCLKDIV = 32768 x (15+1) = 0.524 MHz ; measured :  MHz
 ; =====================================
-            MOV     #8,X
-
     .ELSEIF FREQUENCY = 1
-
 ;            MOV     #100h,&CSCTL0       ; preset DCO = 256 
 ;            MOV     #00B1h,&CSCTL1      ; Set 1MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation
             MOV     #1EFFh,&CSCTL0       ; preset MOD=31, DCO=255  
@@ -319,10 +314,7 @@ CS_SD       .equ 2        ; P8.1
 ;            MOV     #001Fh,&CSCTL2        ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1Fh
                                         ; fCOCLKDIV = 32768 x (31+1) = 1.049 MHz ; measured : 1.046MHz
 ; =====================================
-            MOV     #16,X
-
     .ELSEIF FREQUENCY = 2
-
 ;            MOV     #100h,&CSCTL0       ; preset DCO = 256 
 ;            MOV     #00B3h,&CSCTL1      ; Set 2MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation
             MOV     #1EFFh,&CSCTL0       ; preset MOD=31, DCO=255  
@@ -335,10 +327,7 @@ CS_SD       .equ 2        ; P8.1
 ;            MOV     #003Dh,&CSCTL2        ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=3Dh
                                         ; fCOCLKDIV = 32768 x (61+1) = 2.031 MHz ; measured :  MHz
 ; =====================================
-            MOV     #32,X
-
     .ELSEIF FREQUENCY = 4
-
 ;            MOV     #100h,&CSCTL0       ; preset DCO = 256 
 ;            MOV     #00B5h,&CSCTL1      ; Set 4MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation
             MOV     #1EFFh,&CSCTL0       ; preset MOD=31, DCO=255  
@@ -353,10 +342,7 @@ CS_SD       .equ 2        ; P8.1
 ;            MOV     #007Ah,&CSCTL2      ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=7Ah
                                         ; fCOCLKDIV = 32768 x (122+1) = 4.030 MHz ; measured : 4.020MHz
 ; =====================================
-            MOV     #64,X
-
     .ELSEIF FREQUENCY = 8
-
 ;            MOV     #100h,&CSCTL0       ; preset DCO = 256 
 ;            MOV     #00B7h,&CSCTL1      ; Set 8MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation
             MOV     #1EFFh,&CSCTL0       ; preset MOD=31, DCO=255  
@@ -368,7 +354,6 @@ CS_SD       .equ 2        ; P8.1
                                         ; fCOCLKDIV = 32768 x (243+1) = 7.995 MHz ; measured : 7.976MHz
             MOV     #00F4h,&CSCTL2      ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F4h
                                         ; fCOCLKDIV = 32768 x (244+1) = 8.028 MHz ; measured : 8.009MHz
-
 ;            MOV     #00F5h,&CSCTL2      ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F5h
                                         ; fCOCLKDIV = 32768 x (245+1) = 8.061 MHz ; measured : 8.042MHz
 
@@ -376,10 +361,7 @@ CS_SD       .equ 2        ; P8.1
 ;            MOV     #00FAh,&CSCTL2      ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=FAh
 
 ; =====================================
-            MOV     #128,X
-
     .ELSEIF FREQUENCY = 12
-
 ;            MOV     #100h,&CSCTL0       ; preset DCO = 256 
 ;            MOV     #00B9h,&CSCTL1      ; Set 12MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation
             MOV     #1EFFh,&CSCTL0       ; preset MOD=31, DCO=255  
@@ -394,10 +376,7 @@ CS_SD       .equ 2        ; P8.1
 ;            MOV     #016Fh,&CSCTL2      ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E9h
                                         ; fCOCLKDIV = 32768 x 367+1) = 12.058 MHz ; measured : 12.xxxMHz
 ; =====================================
-            MOV     #192,X
-
     .ELSEIF FREQUENCY = 16
-
 ;            MOV     #100h,&CSCTL0       ; preset DCO = 256 
 ;            MOV     #00BBh,&CSCTL1      ; Set 16MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation
             MOV     #1EFFh,&CSCTL0       ; preset MOD=31, DCO=255  
@@ -412,8 +391,6 @@ CS_SD       .equ 2        ; P8.1
 ;            MOV     #01E9h,&CSCTL2      ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E9h
                                         ; fCOCLKDIV = 32768 x 489+1) = 16.056 MHz ; measured : 16.02MHz
 ; =====================================
-            MOV     #256,X
-
     .ELSEIF
     .error "bad frequency setting, only 0.5,1,2,4,8,12,16 MHz"
     .ENDIF
@@ -421,26 +398,14 @@ CS_SD       .equ 2        ; P8.1
     .IFDEF LF_XTAL
 ;           MOV     #0000h,&CSCTL3      ; FLL select XT1, FLLREFDIV=0 (default value)
             MOV     #0000h,&CSCTL4      ; ACLOCK select XT1, MCLK & SMCLK select DCOCLKDIV
-
             BIS.B   #06,&P4SEL0         ; P4.2 as XOUT, P4.1 as XIN
-
     .ELSE
             BIS     #0010h,&CSCTL3      ; FLL select REFCLOCK
             MOV     #0200h,&CSCTL4      ; ACLOCK select VLOCLK, MCLK & SMCLK select DCOCLKDIV (default value)
     .ENDIF
-
-            BIS &SYSRSTIV,&SAVE_SYSRSTIV; store volatile SYSRSTIV preserving a pending request for DEEP_RST
-;            MOV &SAVE_SYSRSTIV,TOS  ;
-;            CMP #2,TOS              ; POWER ON ?
-;            JZ      ClockWaitX      ; yes
-;            RRUM    #1,X            ; wait only 250 ms
-ClockWaitX  MOV     #5209,Y         ; wait 0.5s before starting after POR
-                                    ;       ...because FLL lock time = 280 ms
-ClockWaitY  SUB     #1,Y            ;1
-            JNZ     ClockWaitY      ;2 5209x3 = 15625 cycles delay = 15.625ms @ 1MHz
-            SUB     #1,X            ; x 32 @ 1 MHZ = 500ms
-            JNZ     ClockWaitX      ; time to stabilize power source ( 500ms )
-
-;WAITFLL     BIT #300h,&CSCTL7       ; wait FLL lock
-;            JNZ WAITFLL
-
+            MOV     #64,X               ; 64* 3 ms = 192 ms delay, because FLL lock time = 120 ms
+ClockWaitX  MOV     &FREQ_KHZ,Y         ;
+ClockWaitY  SUB     #1,Y                ;1
+            JNZ     ClockWaitY          ;2 FREQ_KHZ x 3 ==> 3ms
+            SUB     #1,X                ;
+            JNZ     ClockWaitX          ;