altera works, xilinx works with trivial bugs

[fpga-leon-mjpeg/leon-mjpeg.git] / grlib-gpl-1.0.22-b4095 / designs / leon3-gr-xc3s-1500-mjpeg / .config

diff --git a/grlib-gpl-1.0.22-b4095/designs/leon3-gr-xc3s-1500-mjpeg/.config b/grlib-gpl-1.0.22-b4095/designs/leon3-gr-xc3s-1500-mjpeg/.config
index 2d952b1..a4edbab 100644 (file)
--- a/grlib-gpl-1.0.22-b4095/designs/leon3-gr-xc3s-1500-mjpeg/.config
+++ b/grlib-gpl-1.0.22-b4095/designs/leon3-gr-xc3s-1500-mjpeg/.config
@@ -97,8 +97,8 @@ CONFIG_IU_RSTADDR=00000
 # Cache system
 #
 CONFIG_ICACHE_ENABLE=y
-# CONFIG_ICACHE_ASSO1 is not set
-CONFIG_ICACHE_ASSO2=y
+CONFIG_ICACHE_ASSO1=y
+# CONFIG_ICACHE_ASSO2 is not set
 # CONFIG_ICACHE_ASSO3 is not set
 # CONFIG_ICACHE_ASSO4 is not set
 # CONFIG_ICACHE_SZ1 is not set
@@ -110,12 +110,8 @@ CONFIG_ICACHE_SZ4=y
 # CONFIG_ICACHE_SZ64 is not set
 # CONFIG_ICACHE_SZ128 is not set
 # CONFIG_ICACHE_SZ256 is not set
-# CONFIG_ICACHE_LZ16 is not set
-CONFIG_ICACHE_LZ32=y
-# CONFIG_ICACHE_ALGORND is not set
-# CONFIG_ICACHE_ALGOLRR is not set
-CONFIG_ICACHE_ALGOLRU=y
-# CONFIG_ICACHE_LOCK is not set
+CONFIG_ICACHE_LZ16=y
+# CONFIG_ICACHE_LZ32 is not set
 CONFIG_DCACHE_ENABLE=y
 CONFIG_DCACHE_ASSO1=y
 # CONFIG_DCACHE_ASSO2 is not set