end if;
when others =>
end case;
-
+
-- reset part
- if rst = '0' then
+ if rst = '0' or vstartgen = '1' then
v.hreg.getscan := '0';
v.hreg.rdscan := '0';
v.hreg.getq := '0';
v.hreg.rdoffset := '0';
v.hreg.getval := '0';
v.hreg.rdval := '0';
- v.preg.sampf := '0';
- v.preg.xmcumax := (others => '0');
- v.preg.ymcumax := (others => '0');
- v.preg.incaddy := (others => '0');
- v.preg.incaddmcux := (others => '0');
- v.preg.incaddmcuy := (others => '0');
- v.preg.fbstartadd := (others => '0');
- v.preg.through_bit := '0';
v.fetch_state := memwait;
v.dec_state := standby;
v.fifo_rp := (others => '0');
v.capture := "00";
v.skipcnt := (others => '0');
end if;
+ if rst = '0' then
+ v.preg.sampf := '0';
+ v.preg.xmcumax := (others => '0');
+ v.preg.ymcumax := (others => '0');
+ v.preg.incaddy := (others => '0');
+ v.preg.incaddmcux := (others => '0');
+ v.preg.incaddmcuy := (others => '0');
+ v.preg.fbstartadd := (others => '0');
+ v.preg.through_bit := '0';
+ v.preg.hardonly := '0';
+ end if;
+
-- signals
rin <= v;