use grlib.stdlib.all;
-
-
entity idct1 is
port ( rst : in std_ulogic;
clk : in std_ulogic;
architecture rtl of idct1 is
-
-function stdv2str(vec:std_logic_vector) return string is
- variable str : string(vec'length downto 1);
- begin
- for i in vec'length-1 downto 0 loop
- if(vec(i)='U') then
- str(i+1) := 'U';
- elsif(vec(i)='X') then
- str(i+1) := 'X';
- elsif(vec(i)='0') then
- str(i+1) := '0';
- elsif(vec(i)='1') then
- str(i+1) := '1';
- elsif(vec(i)='Z') then
- str(i+1) := 'Z';
- elsif(vec(i)='W') then
- str(i+1) := 'W';
- elsif(vec(i)='L') then
- str(i+1) := 'L';
- elsif(vec(i)='H') then
- str(i+1) := 'H';
- else
- str(i+1) := '-';
- end if;
- end loop;
- return str;
-end;
-
function mysigned_mul(a,b : std_logic_vector) return std_logic_vector is
variable z : std_logic_vector(a'length + b'length -1 downto 0);
begin
z := std_logic_vector(signed(a) * signed(b));
--- report "a=" & stdv2str(a) severity NOTE;
--- report "a integer =" & integer'image(TO_INTEGER(signed(a))) severity NOTE;
--- report "b=" & stdv2str(b) severity NOTE;
--- report "b integer =" & integer'image(TO_INTEGER(signed(b))) severity NOTE;
--- report "a*b integer =" & integer'image(TO_INTEGER(signed(a))* TO_INTEGER(signed(b))) severity NOTE;
--- report "a*b=" & stdv2str(z) severity NOTE;
return(z);
end;
-
function mysigned_add(a,b : std_logic_vector) return std_logic_vector is
variable ex_a : std_logic_vector(a'length downto 0);
variable ex_b : std_logic_vector(b'length downto 0);
variable tmpdata : std_logic_vector(34 downto 0);
variable z : std_logic_vector(22 downto 0);
begin
--- judge := indata(11);
if (pol = '1') then
tmpdata := (not indata) + 1 ;
else
end;
-
subtype coeff23 is std_logic_vector(22 downto 0);
type coeff_array1 is array(0 to 31) of coeff23;
constant coeff_rom : coeff_array1 :=
"00110000111110111100011","10001001101111100101001","01110110010000011011000","11001111000001000011110",
"00011000111110001011100","10111000111000110001010","01101010011011011001100","10000010011101011010001");
--- d d d d
--- 0 c 6 c
--- 8 3 e 9
--- c 4 1 a
--- d 4 4 d
--- 6 1 c c
--- 3 9 8 e
--- c a c 1
-
type tablereg_type is array (0 to 3) of std_logic_vector(22 downto 0);
type accumulator_type is array (0 to 7) of std_logic_vector(25 downto 0);
type resultreg_type is array (0 to 7) of std_logic_vector(15 downto 0);
-
type d_reg is record
inreg : std_logic_vector(11 downto 0);
--- table_reg : tablereg_type;
accumulator : accumulator_type;
result_reg : resultreg_type;
end record;
control_reg : c_reg;
end record;
-
type node1_array is array (0 to 3) of std_logic_vector(22 downto 0);
type node2_array is array (0 to 3) of std_logic_vector(34 downto 0);
type node3_array is array (0 to 7) of std_logic_vector(22 downto 0);
type node6_array is array (0 to 7) of std_logic_vector(15 downto 0);
signal r, rin : all_reg;
-signal sig_node1_0 : std_logic_vector(22 downto 0);
-signal sig_node2_0 : std_logic_vector(34 downto 0);
-signal sig_node3_0 : std_logic_vector(22 downto 0);
-signal sig_node4_0 : std_logic_vector(25 downto 0);
-signal sig_node5_0 : std_logic_vector(26 downto 0);
-signal sig_node6_0 : std_logic_vector(15 downto 0);
-signal sig_node1_1 : std_logic_vector(22 downto 0);
-signal sig_node2_1 : std_logic_vector(34 downto 0);
-signal sig_node3_6 : std_logic_vector(22 downto 0);
-signal sig_node4_6 : std_logic_vector(25 downto 0);
-signal sig_node5_6 : std_logic_vector(26 downto 0);
-signal sig_node6_6 : std_logic_vector(15 downto 0);
+--signal sig_node1_0 : std_logic_vector(22 downto 0);
+--signal sig_node2_0 : std_logic_vector(34 downto 0);
+--signal sig_node3_0 : std_logic_vector(22 downto 0);
+--signal sig_node4_0 : std_logic_vector(25 downto 0);
+--signal sig_node5_0 : std_logic_vector(26 downto 0);
+--signal sig_node6_0 : std_logic_vector(15 downto 0);
+--signal sig_node1_1 : std_logic_vector(22 downto 0);
+--signal sig_node2_1 : std_logic_vector(34 downto 0);
+--signal sig_node3_6 : std_logic_vector(22 downto 0);
+--signal sig_node4_6 : std_logic_vector(25 downto 0);
+--signal sig_node5_6 : std_logic_vector(26 downto 0);
+--signal sig_node6_6 : std_logic_vector(15 downto 0);
begin
variable node2 : node2_array;
variable node3 : node3_array;
variable node4 : node4_array;
- variable node5 : node5_array;
+ variable node5 : node5_array;
variable node6 : node6_array;
variable pol : std_logic;
-
variable count_num : integer;
variable vstrobe2 : std_logic;
variable vready1 : std_logic;
node1(3) := coeff_rom(3);
end case;
-
--- report "node1_0=" & stdv2str(node1(0)) severity NOTE;
--- report "node1_0 integer =" & integer'image(TO_INTEGER(signed(node1(0)))) severity NOTE;
-
-
for i in 0 to 3 loop
node2(i) := mysigned_mul(node1(i), r.data_reg.inreg);
+-- node2(i) := mysigned_mul23x12(node1(i), r.data_reg.inreg);
node3(i) := round1(node2(i));
end loop;
-
-- when 3 | 5 | 7 | 9 | 11 | 13 | 15 | 17 | 19 | 21 | 23 | ..... | 65
-- when 2 4 6 8 10 12 14 16 18 20 22 64
if((count_num mod 2) = 0 and (count_num >= 2) and (count_num <= 64))then
v.control_reg.counter := (others => '0');
end if;
end if;
--- vready1 := '0';
--- if (ready2 = '1' and v.control_reg.counter = "0000000") then
--- vready1 := '1';
--- end if;
vready1 := '0';
if(ready2 = '1' and count_num <= 63) then
vready1 := '1';
-- signal
outdata <= r.data_reg.result_reg(0);
- strobe2 <= vstrobe2;
- ready1 <= vready1;
+ strobe2 <= vstrobe2;
+ ready1 <= vready1;
rin <= v;
-- debug
- sig_node1_0 <= node1(0);
- sig_node2_0 <= node2(0);
- sig_node3_0 <= node3(0);
- sig_node4_0 <= node4(0);
- sig_node5_0 <= node5(0);
- sig_node6_0 <= node6(0);
-
- sig_node1_1 <= node1(1);
- sig_node2_1 <= node2(1);
- sig_node3_6 <= node3(6);
- sig_node4_6 <= node4(6);
- sig_node5_6 <= node5(6);
- sig_node6_6 <= node6(6);
-
+-- sig_node1_0 <= node1(0);
+-- sig_node2_0 <= node2(0);
+-- sig_node3_0 <= node3(0);
+-- sig_node4_0 <= node4(0);
+-- sig_node5_0 <= node5(0);
+-- sig_node6_0 <= node6(0);
+-- sig_node1_1 <= node1(1);
+-- sig_node2_1 <= node2(1);
+-- sig_node3_6 <= node3(6);
+-- sig_node4_6 <= node4(6);
+-- sig_node5_6 <= node5(6);
+-- sig_node6_6 <= node6(6);
end process;
-- registers
reg : process(clk)
end if;
end process;
-
-
end rtl;
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