altera works, xilinx works with trivial bugs

[fpga-leon-mjpeg/leon-mjpeg.git] / grlib-gpl-1.0.22-b4095 / lib / kuri / mjpeg / idct2.vhd.bak

diff --git a/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/idct2.vhd.bak b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/idct2.vhd.bak
index 44ad1dd..23894eb 100644 (file)
--- a/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/idct2.vhd.bak
+++ b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/idct2.vhd.bak
@@ -148,18 +148,18 @@ type node5_array is array (0 to 7) of std_logic_vector(18 downto 0);
 type node6_array is array (0 to 7) of std_logic_vector(7 downto 0);
        
 signal r, rin : all_reg;
-signal sig_node1_0 : std_logic_vector(16 downto 0);
-signal sig_node2_0 : std_logic_vector(32 downto 0);
-signal sig_node3_0 : std_logic_vector(14 downto 0);
-signal sig_node4_0 : std_logic_vector(17 downto 0);
-signal sig_node5_0 : std_logic_vector(18 downto 0);
-signal sig_node6_0 : std_logic_vector(7 downto 0);
-signal sig_node1_3 : std_logic_vector(16 downto 0);
-signal sig_node2_3 : std_logic_vector(32 downto 0);
-signal sig_node3_4 : std_logic_vector(14 downto 0);
-signal sig_node4_4 : std_logic_vector(17 downto 0);
-signal sig_node5_4 : std_logic_vector(18 downto 0);
-signal sig_node6_4 : std_logic_vector(7 downto 0);
+--signal sig_node1_0 : std_logic_vector(16 downto 0);
+--signal sig_node2_0 : std_logic_vector(32 downto 0);
+--signal sig_node3_0 : std_logic_vector(14 downto 0);
+--signal sig_node4_0 : std_logic_vector(17 downto 0);
+--signal sig_node5_0 : std_logic_vector(18 downto 0);
+--signal sig_node6_0 : std_logic_vector(7 downto 0);
+--signal sig_node1_3 : std_logic_vector(16 downto 0);
+--signal sig_node2_3 : std_logic_vector(32 downto 0);
+--signal sig_node3_4 : std_logic_vector(14 downto 0);
+--signal sig_node4_4 : std_logic_vector(17 downto 0);
+--signal sig_node5_4 : std_logic_vector(18 downto 0);
+--signal sig_node6_4 : std_logic_vector(7 downto 0);
 
 
 begin
@@ -311,21 +311,20 @@ begin
        rin <= v;
 
 -- debug
-   sig_node1_0 <= node1(0);
-   sig_node2_0 <= node2(0);
-   sig_node3_0 <= node3(0);
-   sig_node4_0 <= node4(0);
-   sig_node5_0 <= node5(0);
-   sig_node6_0 <= node6(0);
-sig_node1_3 <= node1(3);
-sig_node2_3 <= node2(3);
-sig_node3_4 <= node3(4);
-sig_node4_4 <= node4(4);
-sig_node5_4 <= node5(4);
-sig_node6_4 <= node6(4);
-
-
+--   sig_node1_0 <= node1(0);
+--   sig_node2_0 <= node2(0);
+--   sig_node3_0 <= node3(0);
+--   sig_node4_0 <= node4(0);
+--   sig_node5_0 <= node5(0);
+--   sig_node6_0 <= node6(0);
+--   sig_node1_3 <= node1(3);
+--   sig_node2_3 <= node2(3);
+--   sig_node3_4 <= node3(4);
+--   sig_node4_4 <= node4(4);
+--   sig_node5_4 <= node5(4);
+--   sig_node6_4 <= node6(4);
 end process;
+
 -- registers
 reg : process(clk)
 begin
@@ -334,7 +333,5 @@ begin
        end if;
 end process;
 
-
-
 end rtl;