coeffin : in std_logic_vector (15 downto 0);
outdata : out std_logic_vector (7 downto 0);
ready2 : in std_logic;
- strobe2 : out std_logic
+ strobe2 : out std_logic;
+ startgen : in std_logic
);
end idct2;
begin
-comb : process(r, rst, strobe1, ready2, coeffin)
+comb : process(r, rst, strobe1, ready2, coeffin, startgen)
variable v : all_reg;
variable node1 : node1_array;
variable node2 : node2_array;
end if;
-- reset part
- if rst = '0' then
+ if rst = '0' or startgen = '1' then
+ v.data_reg.inreg := (others => '0');
for i in 0 to 7 loop
v.data_reg.accumulator(i) := (others => '0');
v.data_reg.result_reg(i) := (others => '0');