altera works, xilinx works with trivial bugs

[fpga-leon-mjpeg/leon-mjpeg.git] / grlib-gpl-1.0.22-b4095 / lib / kuri / mjpeg / mjpeg.vhd.bak

diff --git a/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/mjpeg.vhd.bak b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/mjpeg.vhd.bak
index 5d80a4d..e81c953 100644 (file)
--- a/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/mjpeg.vhd.bak
+++ b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/mjpeg.vhd.bak
@@ -12,10 +12,20 @@ use techmap.gencomp.all;
 
 package mjpeg is
 
-component dctycc is
+type jpg_set_type is record
+  samp_fact : std_logic;
+  xmcumax   : std_logic_vector(5 downto 0);
+  ymcumax   : std_logic_vector(4 downto 0);
+  incaddy   : std_logic_vector(15 downto 0);
+  incaddmcux : std_logic_vector(15 downto 0);
+  incaddmcuy : std_logic_vector(10 downto 0);
+  fbstartadd : std_logic_vector(31 downto 0);
+
+
+
+component huffdctycc is
    generic (
       memtech : integer := DEFMEMTECH;
---      fifo_depth : integer := 32;
       shindex : integer := 0;
       haddr  : integer := 0;
       hmask  : integer := 16#fff#;
@@ -24,7 +34,8 @@ component dctycc is
       paddr  : integer := 0;
       pmask  : integer := 16#fff#;
       mhindex : integer := 0;
-      chprot : integer := 3);
+      chprot : integer := 3);      
+
    port (
       rst   : in std_ulogic;
       clk   : in std_ulogic;
@@ -37,7 +48,47 @@ component dctycc is
    );
 end component;
 
-component dctmem1cont is
+component huff  is
+   generic (
+      memtech : integer := DEFMEMTECH;
+      shindex : integer := 0;
+      haddr  : integer := 0;
+      hmask  : integer := 16#fff#;
+      hirq   : integer := 0;      
+      pindex : integer := 0;
+      paddr  : integer := 0;
+      pmask  : integer := 16#fff#;
+      mhindex : integer := 0;
+      chprot : integer := 3);      
+   port (
+      rst   : in std_ulogic;
+      clk   : in std_ulogic;
+      ahbsi : in ahb_slv_in_type;
+      ahbso : out ahb_slv_out_type;
+      apbi  : in apb_slv_in_type;
+      apbo  : out apb_slv_out_type;
+      kready : in std_logic;
+      kstrobe : out std_logic;
+      kdata   : out std_logic_vector(11 downto 0);
+      kaddress : out std_logic_vector(5 downto 0);
+      samp_fact : out std_logic;
+      error : in std_logic_vector(2 downto 0);
+      xmcumax : out std_logic_vector(5 downto 0);
+      ymcumax : out std_logic_vector(4 downto 0);
+      incaddy : out std_logic_vector(15 downto 0);
+      incaddmcux : out std_logic_vector(15 downto 0);
+      incaddmcuy : out std_logic_vector(10 downto 0);
+      fbstartadd : out std_logic_vector(31 downto 0);
+      startgen : out std_logic;
+      kstrobeq : out std_logic;
+      kdataq : out std_logic_vector(7 downto 0);
+      kaddq : out std_logic_vector(7 downto 0);
+      krddataq : in std_logic_vector(7 downto 0);
+      krdq : out std_logic      
+   );
+end component;
+
+component huffmemcont is
    generic (
       memtech : integer := DEFMEMTECH);
    port (
@@ -45,6 +96,7 @@ component dctmem1cont is
       clk   : in std_ulogic;
       kready1  : out std_logic;
       kstrobe1 : in std_logic;
+      kaddress1 : in std_logic_vector(5 downto 0);
       kdata1   : in std_logic_vector(11 downto 0);
       kready2  : in std_logic;
       kstrobe2 : out std_logic;
@@ -54,6 +106,30 @@ component dctmem1cont is
       samp_fact : in std_logic;
       kstrobeq1 : in std_logic;
       kdataq1   : in std_logic_vector(7 downto 0);
+      kdataq2   : out std_logic_vector(7 downto 0);
+      
+      kaddq : in std_logic_vector(7 downto 0);
+      krdq : in std_logic;
+      krddataq : out std_logic_vector(7 downto 0)
+   );
+end component;
+
+component dctmem1cont is
+   generic (
+      memtech : integer := DEFMEMTECH);
+   port (
+      rst   : in std_ulogic;
+      clk   : in std_ulogic;
+      kready1  : out std_logic;
+      kstrobe1 : in std_logic;
+      kdata1   : in std_logic_vector(11 downto 0);
+      kready2  : in std_logic;
+      kstrobe2 : out std_logic;
+      kdata2   : out std_logic_vector(11 downto 0);
+      error    : out std_logic;
+      samp_fact : in std_logic;
+      kstrobeq1 : in std_logic;
+      kdataq1   : in std_logic_vector(7 downto 0);
       kdataq2   : out std_logic_vector(7 downto 0)
    );
 end component;
@@ -99,30 +175,6 @@ component idct2 is
            );
 end component;
 
-component upycc
-  generic (
-    memtech : integer := DEFMEMTECH;
-    shindex : integer := 0;
-    haddr  : integer := 0;
-    hmask  : integer := 16#fff#;
-    hirq   : integer := 0;      
-    pindex : integer := 0;
-    paddr  : integer := 0;
-    pmask  : integer := 16#fff#;
-    mhindex : integer := 0;
-    chprot : integer := 3);
-   port (
-     rst    : in std_ulogic;
-     clk   : in std_ulogic;
-     ahbmi : in ahb_mst_in_type;
-     ahbmo : out ahb_mst_out_type;
-     ahbsi : in ahb_slv_in_type;
-     ahbso : out ahb_slv_out_type;
-     apbi  : in apb_slv_in_type;
-     apbo  : out apb_slv_out_type
-   );   
-end component;
-
 component yccambaif
      generic (
       memtech : integer := DEFMEMTECH;
@@ -198,30 +250,4 @@ component yccrgb
    );
 end component;
 
-component yccrgbs 
-   generic (
-      memtech : integer := DEFMEMTECH;
-      fifo_depth : integer := 32;
-      shindex : integer := 0;
-      chprot : integer := 3;
-      haddr  : integer := 0;
-      hmask  : integer := 16#fff#;
-      pindex : integer := 0;
-      paddr  : integer := 0;
-      pmask  : integer := 16#fff#;
-      mhindex : integer := 0;
-      hirq   : integer := 0;
-      burst_num : integer := 16);
-   port (
-      rst   : in std_ulogic;
-      clk   : in std_ulogic;
-      ahbmi : in ahb_mst_in_type;
-      ahbmo : out ahb_mst_out_type;
-      ahbsi : in ahb_slv_in_type;
-      ahbso : out ahb_slv_out_type;
-      apbi  : in apb_slv_in_type;
-      apbo  : out apb_slv_out_type
-   );
-end component;   
-    
 end;