change jpeg IPCores. startgen signal distribute into all module

[fpga-leon-mjpeg/leon-mjpeg.git] / grlib-gpl-1.0.22-b4095 / lib / kuri / mjpeg / mjpeg.vhd

diff --git a/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/mjpeg.vhd b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/mjpeg.vhd
index e23a78b..21dc7d9 100644 (file)
--- a/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/mjpeg.vhd
+++ b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/mjpeg.vhd
@@ -120,15 +120,14 @@ component huffmemcont is
       kstrobe2 : out std_logic;
       kdata2   : out std_logic_vector(11 downto 0);
       error    : out std_logic;
-
       samp_fact : in std_logic;
       kstrobeq1 : in std_logic;
       kdataq1   : in std_logic_vector(7 downto 0);
-      kdataq2   : out std_logic_vector(7 downto 0);
-      
+      kdataq2   : out std_logic_vector(7 downto 0);      
       kaddq : in std_logic_vector(7 downto 0);
       krdq : in std_logic;
-      krddataq : out std_logic_vector(7 downto 0)
+      krddataq : out std_logic_vector(7 downto 0);
+      startgen : in std_logic
    );
 end component;
 
@@ -164,7 +163,8 @@ component dctmem2cont is
       kready2  : in std_logic;
       kstrobe2 : out std_logic;
       kdata2   : out std_logic_vector(15 downto 0);
-      error     : out std_logic
+      error     : out std_logic;
+      startgen  : in std_logic
    );
 end component;
 
@@ -177,7 +177,8 @@ component idct1 is
            quantin : in  std_logic_vector (7 downto 0);
            outdata : out  std_logic_vector (15 downto 0);
            ready2 : in std_logic;
-           strobe2 : out std_logic
+           strobe2 : out std_logic;
+           startgen : in std_logic
            );
 end component;
 
@@ -189,7 +190,8 @@ component idct2 is
            coeffin : in  std_logic_vector (15 downto 0);
            outdata : out  std_logic_vector (7 downto 0);
            ready2 : in std_logic;
-           strobe2 : out std_logic
+           strobe2 : out std_logic;
+           startgen : in std_logic
            );
 end component;
 
@@ -240,7 +242,8 @@ component yccmemcont
       kstrobe2 : out std_logic;
       kdata2   : out std_logic_vector(23 downto 0);
       samp_fact : in std_logic;
-      error     : out std_logic
+      error     : out std_logic;
+      startgen  : in std_logic
    );
 end component;