+++ /dev/null
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.numeric_std.all;\r
-\r
-library grlib;\r
---use grlib.amba.all;\r
-use grlib.stdlib.all;\r
-use grlib.devices.all;\r
-\r
-library techmap;\r
-use techmap.gencomp.all;\r
-\r
-entity yccmemcont is\r
- generic (\r
- memtech : integer := DEFMEMTECH);\r
- port (\r
- rst : in std_ulogic;\r
- clk : in std_ulogic;\r
- kready1 : out std_logic;\r
- kstrobe1 : in std_logic;\r
- kdata1 : in std_logic_vector(7 downto 0);\r
- kready2 : in std_logic;\r
- kstrobe2 : out std_logic;\r
- kdata2 : out std_logic_vector(23 downto 0);\r
- samp_fact : in std_logic;\r
- error : out std_logic\r
- );\r
-end;\r
--- samp_fact = 0 -> 4:1:1\r
--- samp_fact = 1 -> 4:2:2\r
-\r
-\r
-architecture rtl of yccmemcont is\r
-\r
-function stdv2str(vec:std_logic_vector) return string is\r
- variable str : string(vec'length downto 1);\r
- begin\r
- for i in vec'length-1 downto 0 loop\r
- if(vec(i)='U') then\r
- str(i+1) := 'U';\r
- elsif(vec(i)='X') then\r
- str(i+1) := 'X';\r
- elsif(vec(i)='0') then\r
- str(i+1) := '0';\r
- elsif(vec(i)='1') then\r
- str(i+1) := '1';\r
- elsif(vec(i)='Z') then\r
- str(i+1) := 'Z';\r
- elsif(vec(i)='W') then\r
- str(i+1) := 'W';\r
- elsif(vec(i)='L') then\r
- str(i+1) := 'L';\r
- elsif(vec(i)='H') then\r
- str(i+1) := 'H';\r
- else\r
- str(i+1) := '-';\r
- end if;\r
- end loop;\r
- return str;\r
-end; \r
- \r
-type sstate_type is (mem0, mem1);\r
-type mstate_type is (empty, writing, full, reading, standby);\r
-\r
-type control_reg is record\r
- swf : sstate_type;\r
- swb : sstate_type;\r
- mem0state : mstate_type;\r
- mem1state : mstate_type;\r
- countf : std_logic_vector(8 downto 0);\r
--- selectf : std_logic_vector(1 downto 0);\r
- countb : std_logic_vector(7 downto 0);\r
--- countby : std_logic_vector(7 downto 0);\r
--- countbcb : std_logic_vector(7 downto 0);\r
--- countbcr : std_logic_vector(7 downto 0);\r
- stb2keep : std_logic;\r
-end record;\r
-\r
-signal r, rin : control_reg;\r
-signal y0address, y1address : std_logic_vector(7 downto 0);\r
-signal cb0address, cb1address, cr0address, cr1address : std_logic_vector(6 downto 0);\r
-signal y0datain, y1datain, cb0datain, cb1datain, cr0datain, cr1datain : std_logic_vector(7 downto 0);\r
-signal y0dataout, y1dataout, cb0dataout, cb1dataout, cr0dataout, cr1dataout : std_logic_vector(7 downto 0);\r
-signal y0enable, y1enable, cb0enable, cb1enable, cr0enable, cr1enable : std_logic;\r
-signal y0write, y1write, cb0write, cb1write, cr0write, cr1write : std_logic;\r
-\r
-begin\r
-yram0 : syncram generic map(tech => memtech, abits => 8, dbits => 8)\r
- port map( clk, y0address, y0datain, y0dataout, y0enable, y0write);\r
-yram1 : syncram generic map(tech => memtech, abits => 8, dbits => 8)\r
- port map( clk, y1address, y1datain, y1dataout, y1enable, y1write);\r
-cbram0 : syncram generic map(tech => memtech, abits => 7, dbits => 8)\r
- port map( clk, cb0address, cb0datain, cb0dataout, cb0enable, cb0write);\r
-cbram1 : syncram generic map(tech => memtech, abits => 7, dbits => 8)\r
- port map( clk, cb1address, cb1datain, cb1dataout, cb1enable, cb1write);\r
-crram0 : syncram generic map(tech => memtech, abits => 7, dbits => 8)\r
- port map( clk, cr0address, cr0datain, cr0dataout, cr0enable, cr0write);\r
-crram1 : syncram generic map(tech => memtech, abits => 7, dbits => 8)\r
- port map( clk, cr1address, cr1datain, cr1dataout, cr1enable, cr1write); \r
- \r
- \r
-comb : process (r, rst, kstrobe1, kdata1, kready2, samp_fact, y0dataout, y1dataout, \r
- cb0dataout, cb1dataout, cr0dataout, cr1dataout)\r
- variable v : control_reg; \r
- variable vkready1 : std_logic;\r
- variable verror : std_logic;\r
- variable vy0address, vy1address : std_logic_vector(7 downto 0);\r
- variable vcb0address, vcb1address, vcr0address, vcr1address : std_logic_vector(6 downto 0);\r
--- variable vy0datain, vy1datain, vcb0datain, vcb1datain, vcr0datain, vcr1datain \r
--- : std_logic_vector(7 downto 0);\r
- variable vy0enable, vy1enable, vcb0enable, vcb1enable, vcr0enable, vcr1enable \r
- : std_logic;\r
- variable vy0write, vy1write, vcb0write, vcb1write, vcr0write, vcr1write : std_logic;\r
- variable fcountup, bcountup : std_logic;\r
- variable fcntint : integer;\r
- variable vstrobe : std_logic;\r
- variable outdata : std_logic_vector(23 downto 0);\r
- begin\r
-\r
- v := r;\r
- verror := '0';\r
- vy0enable := '0'; vy1enable := '0'; vcb0enable := '0'; vcb1enable := '0'; vcr0enable := '0'; vcr1enable := '0';\r
- vy0write := '0'; vy1write := '0'; vcb0write := '0'; vcb1write := '0'; vcr0write := '0'; vcr1write := '0';\r
- fcountup := '0'; bcountup := '0';\r
- vy0address := (others => '0'); vy1address := (others => '0'); \r
- vcb0address := (others => '0'); vcb1address := (others => '0');\r
- vcr0address := (others => '0'); vcr1address := (others => '0');\r
- \r
- -- forward part\r
- fcntint := to_integer(unsigned(r.countf));\r
- if (kstrobe1 = '1') then\r
- if ((r.swf = mem0 and (r.mem0state = full or r.mem0state = reading))or\r
- (r.swf = mem1 and (r.mem1state = full or r.mem1state = reading)))then\r
- verror := '1'; \r
- end if;\r
- fcountup := '1';\r
- if(r.swf = mem0) then\r
- if(samp_fact = '0') then\r
- if(fcntint < 256) then\r
- vy0enable := '1';\r
- vy0write := '1';\r
- vy0address := r.countf(7 downto 0);\r
- elsif(fcntint < 320) then\r
- vcb0enable := '1';\r
- vcb0write := '1';\r
- vcb0address := r.countf(6 downto 0);\r
- elsif(fcntint < 384) then\r
- vcr0enable := '1';\r
- vcr0write := '1';\r
- vcr0address := '0' & r.countf(5 downto 0);\r
- else\r
- verror := '1';\r
- end if;\r
- else\r
- if(fcntint < 256) then\r
- vy0enable := '1';\r
- vy0write := '1';\r
- vy0address := r.countf(7 downto 0);\r
- elsif(fcntint < 384) then\r
- vcb0enable := '1';\r
- vcb0write := '1';\r
- vcb0address := r.countf(6 downto 0);\r
- elsif(fcntint < 512) then\r
- vcr0enable := '1';\r
- vcr0write := '1';\r
- vcr0address := r.countf(6 downto 0);\r
- else\r
- verror := '1';\r
- end if; \r
- end if;\r
- else\r
- if(samp_fact = '0') then\r
- if(fcntint < 256) then\r
- vy1enable := '1';\r
- vy1write := '1';\r
- vy1address := r.countf(7 downto 0);\r
- elsif(fcntint < 320) then\r
- vcb1enable := '1';\r
- vcb1write := '1';\r
- vcb1address := r.countf(6 downto 0);\r
- elsif(fcntint < 384) then\r
- vcr1enable := '1';\r
- vcr1write := '1';\r
- vcr1address := '0' & r.countf(5 downto 0);\r
- else\r
- verror := '1';\r
- end if;\r
- else\r
- if(fcntint < 256) then\r
- vy1enable := '1';\r
- vy1write := '1';\r
- vy1address := r.countf(7 downto 0);\r
- elsif(fcntint < 384) then\r
- vcb1enable := '1';\r
- vcb1write := '1';\r
- vcb1address := r.countf(6 downto 0);\r
- elsif(fcntint < 512) then\r
- vcr1enable := '1';\r
- vcr1write := '1';\r
- vcr1address := r.countf(6 downto 0);\r
- else\r
- verror := '1';\r
- end if; \r
- end if;\r
- end if; \r
- end if;\r
- \r
- vkready1 := '0';\r
- if (r.swf = mem0 and (r.mem0state = empty or r.mem0state = writing)) or (r.swf = mem1 and (r.mem1state = empty or r.mem1state = writing)) then\r
- vkready1 := '1';\r
- end if;\r
- \r
- --backward part\r
- v.stb2keep := '0'; \r
- if (kready2 = '1') then\r
- if(r.swb = mem0 and (r.mem0state = full or r.mem0state = reading)) then\r
- bcountup := '1';\r
- v.stb2keep := '1';\r
- vy0enable := '1'; \r
- vcb0enable := '1';\r
- vcr0enable := '1';\r
- vy0address := r.countb(7) & r.countb(3) & r.countb(6 downto 4) & r.countb(2 downto 0);\r
- if(samp_fact = '0') then \r
- vcb0address := '0' & r.countb(7 downto 5) & r.countb(3 downto 1);\r
- vcr0address := '0' & r.countb(7 downto 5) & r.countb(3 downto 1);\r
- else\r
- vcb0address := r.countb(7 downto 1); \r
- vcr0address := r.countb(7 downto 1);\r
- end if;\r
- elsif(r.swb = mem1 and (r.mem1state = full or r.mem1state = reading))then\r
- bcountup := '1';\r
- v.stb2keep := '1';\r
- vy1enable := '1';\r
- vcb1enable := '1';\r
- vcr1enable := '1';\r
- vy1address := r.countb(7) & r.countb(3) & r.countb(6 downto 4) & r.countb(2 downto 0);\r
- if(samp_fact = '0') then \r
- vcb1address := '0' & r.countb(7 downto 5) & r.countb(3 downto 1);\r
- vcr1address := '0' & r.countb(7 downto 5) & r.countb(3 downto 1);\r
- else\r
- vcb1address := r.countb(7 downto 1); \r
- vcr1address := r.countb(7 downto 1);\r
- end if;\r
- end if;\r
- end if;\r
- \r
- if(r.swb = mem0)then\r
- outdata := y0dataout & cb0dataout & cr0dataout;\r
- else\r
- outdata := y1dataout & cb1dataout & cr1dataout;\r
- end if;\r
- \r
- \r
- --state-machine\r
- --check empty case batting memory read write access\r
- \r
-\r
- case r.mem0state is\r
- when empty =>\r
- if (r.swf = mem0 and fcountup = '1') then\r
- v.mem0state := writing;\r
- end if;\r
- when writing =>\r
- if ((samp_fact = '0' and fcntint = 383 and fcountup = '1')or(samp_fact = '1' and fcntint = 511 and fcountup = '1')) then\r
- v.mem0state := full; \r
- v.swf := mem1;\r
- end if;\r
- when full => \r
- if (r.swb = mem0 and kready2 = '1') then\r
- v.mem0state := reading;\r
- end if;\r
- when reading =>\r
- if (r.countb = "11111111") then\r
- v.mem0state := standby;\r
- end if;\r
- when standby => \r
- v.swb := mem1;\r
- v.mem0state := empty;\r
- when others =>\r
- end case;\r
- \r
- case r.mem1state is\r
- when empty =>\r
- if (r.swf = mem1 and fcountup = '1') then\r
- v.mem1state := writing;\r
- end if;\r
- when writing =>\r
- if ((samp_fact = '0' and fcntint = 383 and fcountup = '1')or(samp_fact = '1' and fcntint = 511 and fcountup = '1')) then\r
- v.mem1state := full; \r
- v.swf := mem0;\r
- end if;\r
- when full => \r
- if (r.swb = mem1 and kready2 = '1') then\r
- v.mem1state := reading;\r
- end if;\r
- when reading =>\r
- if (r.countb = "11111111") then\r
- v.mem1state := standby;\r
- end if;\r
- when standby =>\r
- v.swb := mem0;\r
- v.mem1state := empty;\r
- when others =>\r
- end case; \r
-\r
--- counter\r
- if(fcountup = '1') then\r
- v.countf := r.countf + '1';\r
- if (samp_fact = '0') and (fcntint = 383) then\r
- v.countf := "000000000";\r
- elsif (samp_fact = '1') and (fcntint = 511) then\r
- v.countf := "000000000";\r
- end if; \r
- end if;\r
- if (bcountup = '1') then\r
- v.countb := r.countb + '1';\r
- end if;\r
- \r
--- reset part\r
- if rst = '0' then\r
- v.swf := mem0;\r
- v.swb := mem0;\r
- v.mem0state := empty;\r
- v.mem1state := empty;\r
- v.countf := (others => '0');\r
- v.countb := (others => '0');\r
- v.stb2keep := '0';\r
- end if;\r
- \r
--- signal\r
-\r
- rin <= v; \r
- kready1 <= vkready1;\r
- kstrobe2 <= r.stb2keep;\r
- kdata2 <= outdata;\r
- error <= verror;\r
- y0address <= vy0address;\r
- y1address <= vy1address;\r
- cb0address <= vcb0address;\r
- cb1address <= vcb1address;\r
- cr0address <= vcr0address;\r
- cr1address <= vcr1address;\r
- y0enable <= vy0enable;\r
- y1enable <= vy1enable;\r
- cb0enable <= vcb0enable;\r
- cb1enable <= vcb1enable;\r
- cr0enable <= vcr0enable;\r
- cr1enable <= vcr1enable;\r
- y0write <= vy0write;\r
- y1write <= vy1write;\r
- cb0write <= vcb0write;\r
- cb1write <= vcb1write;\r
- cr0write <= vcr0write;\r
- cr1write <= vcr1write;\r
- \r
-end process;\r
-\r
- y0datain <= kdata1;\r
- y1datain <= kdata1;\r
- cb0datain <= kdata1;\r
- cb1datain <= kdata1;\r
- cr0datain <= kdata1;\r
- cr1datain <= kdata1;\r
- \r
--- registers \r
-reg : process(clk)\r
-begin\r
- if rising_edge(clk) then\r
- r <= rin;\r
- end if;\r
-end process;\r
-\r
-\r
-end;\r
-
\ No newline at end of file
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