From db1a2194c3e50c1d0f9d651e0951844c218b29b3 Mon Sep 17 00:00:00 2001 From: Kenichi Kurimoto Date: Wed, 5 Jan 2011 16:39:32 +0900 Subject: [PATCH] change BLANCA top module to insert 3stage FF just before SDRAM DLL --- grlib-gpl-1.0.22-b4095/designs/BLANCA-AVP/leon3mp.vhd | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/grlib-gpl-1.0.22-b4095/designs/BLANCA-AVP/leon3mp.vhd b/grlib-gpl-1.0.22-b4095/designs/BLANCA-AVP/leon3mp.vhd index b8f76afb..4ab6a47e 100644 --- a/grlib-gpl-1.0.22-b4095/designs/BLANCA-AVP/leon3mp.vhd +++ b/grlib-gpl-1.0.22-b4095/designs/BLANCA-AVP/leon3mp.vhd @@ -46,6 +46,11 @@ use gaisler.ata.all; library esa; use esa.memoryctrl.all; +-- pragma translate_off +library unisim; +use unisim.BUFG; +use unisim.DCM; +-- pragma translate_on use work.config.all; @@ -322,7 +327,7 @@ signal clk_sel : std_logic_vector(1 downto 0); signal sdckesig : std_ulogic; signal uart_ensig : std_ulogic; signal sdclkl2 : std_ulogic; -signal sddll_rst : std_ulogic; +signal sddll_rst : std_logic_vector(0 to 3); signal sigzero : std_logic; signal fbackdll : std_ulogic; signal erx_clk2 : std_ulogic; @@ -356,11 +361,19 @@ begin port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo, open, clk50); sigzero <= '0'; - sddll_rst <= not cgo.clklock; +-- sddll_rst <= not cgo.clklock; + +rstdff : process(sdclkl, cgo.clklock) +begin + if cgo.clklock = '0' then sddll_rst <= (others => '1'); + elsif rising_edge(sdclkl) then + sddll_rst <= sddll_rst(1 to 3) & '0'; + end if; +end process; dllsdclk : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2, CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => -60) port map ( CLKIN => sdclkl, CLKFB => fbackdll, DSSEN => sigzero, PSCLK => sigzero, - PSEN => sigzero, PSINCDEC => sigzero, RST => sddll_rst, CLK0 => fbackdll, + PSEN => sigzero, PSINCDEC => sigzero, RST => sddll_rst(0), CLK0 => fbackdll, CLKFX => sdclkl2, CLK2X => open, CLKFX180 => open, LOCKED => open); --sdclkl2 <= not sdclkl; -- 2.11.0