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[immortalwrt/immortalwrt.git] / target / linux / ipq806x / patches-5.15 / 083-ipq8064-dtsi-additions.patch
1 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
2 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
3 @@ -10,6 +10,8 @@
4  #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
5  #include <dt-bindings/soc/qcom,gsbi.h>
6  #include <dt-bindings/interrupt-controller/arm-gic.h>
7 +#include <dt-bindings/mfd/qcom-rpm.h>
8 +#include <dt-bindings/clock/qcom,rpmcc.h>
9  
10  / {
11         #address-cells = <1>;
12 @@ -30,6 +32,16 @@
13                         next-level-cache = <&L2>;
14                         qcom,acc = <&acc0>;
15                         qcom,saw = <&saw0>;
16 +                       clocks = <&kraitcc 0>, <&kraitcc 4>;
17 +                       clock-names = "cpu", "l2";
18 +                       clock-latency = <100000>;
19 +                       cpu-supply = <&smb208_s2a>;
20 +                       operating-points-v2 = <&opp_table0>;
21 +                       voltage-tolerance = <5>;
22 +                       cooling-min-state = <0>;
23 +                       cooling-max-state = <10>;
24 +                       #cooling-cells = <2>;
25 +                       cpu-idle-states = <&CPU_SPC>;
26                 };
27  
28                 cpu1: cpu@1 {
29 @@ -40,11 +52,125 @@
30                         next-level-cache = <&L2>;
31                         qcom,acc = <&acc1>;
32                         qcom,saw = <&saw1>;
33 +                       clocks = <&kraitcc 1>, <&kraitcc 4>;
34 +                       clock-names = "cpu", "l2";
35 +                       clock-latency = <100000>;
36 +                       cpu-supply = <&smb208_s2b>;
37 +                       operating-points-v2 = <&opp_table0>;
38 +                       voltage-tolerance = <5>;
39 +                       cooling-min-state = <0>;
40 +                       cooling-max-state = <10>;
41 +                       #cooling-cells = <2>;
42 +                       cpu-idle-states = <&CPU_SPC>;
43 +               };
44 +
45 +               idle-states {
46 +                       CPU_SPC: spc {
47 +                               compatible = "qcom,idle-state-spc";
48 +                               status = "disabled";
49 +                               entry-latency-us = <400>;
50 +                               exit-latency-us = <900>;
51 +                               min-residency-us = <3000>;
52 +                       };
53                 };
54 +       };
55  
56 -               L2: l2-cache {
57 -                       compatible = "cache";
58 -                       cache-level = <2>;
59 +       opp_table_l2: opp_table_l2 {
60 +               compatible = "operating-points-v2";
61 +
62 +               opp-384000000 {
63 +                       opp-hz = /bits/ 64 <384000000>;
64 +                       opp-microvolt = <1100000>;
65 +                       clock-latency-ns = <100000>;
66 +                       opp-level = <0>;
67 +               };
68 +
69 +               opp-1000000000 {
70 +                       opp-hz = /bits/ 64 <1000000000>;
71 +                       opp-microvolt = <1100000>;
72 +                       clock-latency-ns = <100000>;
73 +                       opp-level = <1>;
74 +               };
75 +
76 +               opp-1200000000 {
77 +                       opp-hz = /bits/ 64 <1200000000>;
78 +                       opp-microvolt = <1150000>;
79 +                       clock-latency-ns = <100000>;
80 +                       opp-level = <2>;
81 +               };
82 +       };
83 +
84 +       opp_table0: opp_table0 {
85 +               compatible = "operating-points-v2-kryo-cpu";
86 +               nvmem-cells = <&speedbin_efuse>;
87 +
88 +               /*
89 +                * Voltage thresholds are <target min max>
90 +                */
91 +               opp-384000000 {
92 +                       opp-hz = /bits/ 64 <384000000>;
93 +                       opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
94 +                       opp-microvolt-speed0-pvs1-v0 = <925000 878750 971250>;
95 +                       opp-microvolt-speed0-pvs2-v0 = <875000 831250 918750>;
96 +                       opp-microvolt-speed0-pvs3-v0 = <800000 760000 840000>;
97 +                       opp-supported-hw = <0x1>;
98 +                       clock-latency-ns = <100000>;
99 +                       opp-level = <0>;
100 +               };
101 +
102 +               opp-600000000 {
103 +                       opp-hz = /bits/ 64 <600000000>;
104 +                       opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
105 +                       opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;
106 +                       opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;
107 +                       opp-microvolt-speed0-pvs3-v0 = <850000 807500 892500>;
108 +                       opp-supported-hw = <0x1>;
109 +                       clock-latency-ns = <100000>;
110 +                       opp-level = <1>;
111 +               };
112 +
113 +               opp-800000000 {
114 +                       opp-hz = /bits/ 64 <800000000>;
115 +                       opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
116 +                       opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
117 +                       opp-microvolt-speed0-pvs2-v0 = <995000 945250 1044750>;
118 +                       opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;
119 +                       opp-supported-hw = <0x1>;
120 +                       clock-latency-ns = <100000>;
121 +                       opp-level = <1>;
122 +               };
123 +
124 +               opp-1000000000 {
125 +                       opp-hz = /bits/ 64 <1000000000>;
126 +                       opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>;
127 +                       opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
128 +                       opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>;
129 +                       opp-microvolt-speed0-pvs3-v0 = <950000 902500 997500>;
130 +                       opp-supported-hw = <0x1>;
131 +                       clock-latency-ns = <100000>;
132 +                       opp-level = <1>;
133 +               };
134 +
135 +               opp-1200000000 {
136 +                       opp-hz = /bits/ 64 <1200000000>;
137 +                       opp-microvolt-speed0-pvs0-v0 = <1200000 1140000 1260000>;
138 +                       opp-microvolt-speed0-pvs1-v0 = <1125000 1068750 1181250>;
139 +                       opp-microvolt-speed0-pvs2-v0 = <1075000 1021250 1128750>;
140 +                       opp-microvolt-speed0-pvs3-v0 = <1000000 950000 1050000>;
141 +                       opp-supported-hw = <0x1>;
142 +                       clock-latency-ns = <100000>;
143 +                       opp-level = <2>;
144 +               };
145 +
146 +               opp-1400000000 {
147 +                       opp-hz = /bits/ 64 <1400000000>;
148 +                       opp-microvolt-speed0-pvs0-v0 = <1250000 1187500 1312500>;
149 +                       opp-microvolt-speed0-pvs1-v0 = <1175000 1116250 1233750>;
150 +                       opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;
151 +                       opp-microvolt-speed0-pvs3-v0 = <1050000 997500 1102500>;
152 +                       opp-supported-hw = <0x1>;
153 +                       clock-latency-ns = <100000>;
154 +                       opp-level = <2>;
155                 };
156         };
157  
158 @@ -317,6 +443,15 @@
159                 };
160         };
161  
162 +       fab-scaling {
163 +               compatible = "qcom,fab-scaling";
164 +               clocks = <&rpmcc RPM_APPS_FABRIC_A_CLK>, <&rpmcc RPM_EBI1_A_CLK>;
165 +               clock-names = "apps-fab-clk", "ddr-fab-clk";
166 +               fab_freq_high = <533000000>;
167 +               fab_freq_nominal = <400000000>;
168 +               cpu_freq_threshold = <1000000000>;
169 +       };
170 +
171         firmware {
172                 scm {
173                         compatible = "qcom,scm-ipq806x", "qcom,scm";
174 @@ -384,6 +519,15 @@
175                                 };
176                         };
177  
178 +                       i2c4_pins: i2c4_pinmux {
179 +                               mux {
180 +                                       pins = "gpio12", "gpio13";
181 +                                       function = "gsbi4";
182 +                                       drive-strength = <12>;
183 +                                       bias-disable;
184 +                               };
185 +                       };
186 +
187                         spi_pins: spi_pins {
188                                 mux {
189                                         pins = "gpio18", "gpio19", "gpio21";
190 @@ -437,6 +581,27 @@
191                                         bias-bus-hold;
192                                 };
193                         };
194 +
195 +                       mdio0_pins: mdio0_pins {
196 +                               mux {
197 +                                       pins = "gpio0", "gpio1";
198 +                                       function = "mdio";
199 +                                       drive-strength = <8>;
200 +                                       bias-disable;
201 +                               };
202 +                       };
203 +
204 +                       rgmii2_pins: rgmii2_pins {
205 +                               mux {
206 +                                       pins = "gpio27", "gpio28", "gpio29",
207 +                                              "gpio30", "gpio31", "gpio32",
208 +                                              "gpio51", "gpio52", "gpio59",
209 +                                              "gpio60", "gpio61", "gpio62";
210 +                                       function = "rgmii2";
211 +                                       drive-strength = <8>;
212 +                                       bias-disable;
213 +                               };
214 +                       };
215                 };
216  
217                 intc: interrupt-controller@2000000 {
218 @@ -513,6 +678,17 @@
219                         regulator;
220                 };
221  
222 +               saw_l2: regulator@02012000 {
223 +                       compatible = "qcom,saw2", "syscon";
224 +                       reg = <0x02012000 0x1000>;
225 +                       regulator;
226 +               };
227 +
228 +               sic_non_secure: sic-non-secure@12100000 {
229 +                       compatible = "syscon";
230 +                       reg = <0x12100000 0x10000>;
231 +               };
232 +
233                 gsbi2: gsbi@12480000 {
234                         compatible = "qcom,gsbi-v1.0.0";
235                         cell-index = <2>;
236 @@ -568,6 +910,33 @@
237                         };
238                 };
239  
240 +               gsbi6: gsbi@16500000 {
241 +                       status = "disabled";
242 +                       compatible = "qcom,gsbi-v1.0.0";
243 +                       cell-index = <6>;
244 +                       reg = <0x16500000 0x100>;
245 +                       clocks = <&gcc GSBI6_H_CLK>;
246 +                       clock-names = "iface";
247 +                       #address-cells = <1>;
248 +                       #size-cells = <1>;
249 +                       ranges;
250 +
251 +                       syscon-tcsr = <&tcsr>;
252 +
253 +                       gsbi6_i2c: i2c@16580000 {
254 +                               compatible = "qcom,i2c-qup-v1.1.1";
255 +                               reg = <0x16580000 0x1000>;
256 +                               interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
257 +
258 +                               clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
259 +                               clock-names = "core", "iface";
260 +                               status = "disabled";
261 +
262 +                               #address-cells = <1>;
263 +                               #size-cells = <0>;
264 +                       };
265 +               };
266 +
267                 gsbi7: gsbi@16600000 {
268                         status = "disabled";
269                         compatible = "qcom,gsbi-v1.0.0";
270 @@ -589,6 +958,19 @@
271                                 clock-names = "core", "iface";
272                                 status = "disabled";
273                         };
274 +
275 +                       gsbi7_i2c: i2c@16680000 {
276 +                               compatible = "qcom,i2c-qup-v1.1.1";
277 +                               reg = <0x16680000 0x1000>;
278 +                               interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
279 +
280 +                               clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
281 +                               clock-names = "core", "iface";
282 +                               status = "disabled";
283 +
284 +                               #address-cells = <1>;
285 +                               #size-cells = <0>;
286 +                       };
287                 };
288  
289                 sata_phy: sata-phy@1b400000 {
290 @@ -761,6 +937,17 @@
291                         };
292                 };
293  
294 +               L2: l2-cache {
295 +                       compatible = "qcom,krait-cache", "cache";
296 +                       cache-level = <2>;
297 +                       qcom,saw = <&saw_l2>;
298 +
299 +                       clocks = <&kraitcc 4>;
300 +                       clock-names = "l2";
301 +                       l2-supply = <&smb208_s1a>;
302 +                       operating-points-v2 = <&opp_table_l2>;
303 +               };
304 +
305                 rpm: rpm@108000 {
306                         compatible = "qcom,rpm-ipq8064";
307                         reg = <0x108000 0x1000>;
308 @@ -828,6 +1015,11 @@
309                         clock-output-names = "acpu_l2_aux";
310                 };
311  
312 +               kraitcc: clock-controller {
313 +                       compatible = "qcom,krait-cc-v1";
314 +                       #clock-cells = <1>;
315 +               };
316 +
317                 lcc: clock-controller@28000000 {
318                         compatible = "qcom,lcc-ipq8064";
319                         reg = <0x28000000 0x1000>;
320 @@ -835,6 +1027,11 @@
321                         #reset-cells = <1>;
322                 };
323  
324 +               sfpb_mutex_block: syscon@1200600 {
325 +                       compatible = "syscon";
326 +                       reg = <0x01200600 0x100>;
327 +               };
328 +
329                 pcie0: pci@1b500000 {
330                         compatible = "qcom,pcie-ipq8064";
331                         reg = <0x1b500000 0x1000
332 @@ -1188,6 +1385,21 @@
333                         };
334                 };
335  
336 +
337 +               mdio0: mdio@37000000 {
338 +                       #address-cells = <1>;
339 +                       #size-cells = <0>;
340 +
341 +                       compatible = "qcom,ipq8064-mdio", "syscon";
342 +                       reg = <0x37000000 0x200000>;
343 +                       resets = <&gcc GMAC_CORE1_RESET>;
344 +                       reset-names = "stmmaceth";
345 +                       clocks = <&gcc GMAC_CORE1_CLK>;
346 +                       clock-names = "stmmaceth";
347 +
348 +                       status = "disabled";
349 +               };
350 +
351                 vsdcc_fixed: vsdcc-regulator {
352                         compatible = "regulator-fixed";
353                         regulator-name = "SDCC Power";
354 @@ -1262,4 +1474,17 @@
355                         };
356                 };
357         };
358 +
359 +       sfpb_mutex: sfpb-mutex {
360 +               compatible = "qcom,sfpb-mutex";
361 +               syscon = <&sfpb_mutex_block 4 4>;
362 +
363 +               #hwlock-cells = <1>;
364 +       };
365 +
366 +       smem {
367 +               compatible = "qcom,smem";
368 +               memory-region = <&smem>;
369 +               hwlocks = <&sfpb_mutex 3>;
370 +       };
371  };