OSDN Git Service

rockchip: remove kernel 5.10 support
authorTianling Shen <cnsztl@immortalwrt.org>
Fri, 20 May 2022 10:51:34 +0000 (18:51 +0800)
committerTianling Shen <cnsztl@immortalwrt.org>
Fri, 20 May 2022 10:51:34 +0000 (18:51 +0800)
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
30 files changed:
target/linux/rockchip/Makefile
target/linux/rockchip/armv8/config-5.10 [deleted file]
target/linux/rockchip/files/drivers/net/phy/motorcomm.c
target/linux/rockchip/modules.mk
target/linux/rockchip/patches-5.10/005-rockchip-rk3328-add-compatible-to-NanoPi-R2S-etherne.patch [deleted file]
target/linux/rockchip/patches-5.10/006-v5.13-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch [deleted file]
target/linux/rockchip/patches-5.10/007-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch [deleted file]
target/linux/rockchip/patches-5.10/100-rockchip-use-system-LED-for-OpenWrt.patch [deleted file]
target/linux/rockchip/patches-5.10/101-dts-rockchip-add-usb3-controller-node-for-RK3328-SoCs.patch [deleted file]
target/linux/rockchip/patches-5.10/102-rockchip-enable-LAN-port-on-NanoPi-R2S.patch [deleted file]
target/linux/rockchip/patches-5.10/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch [deleted file]
target/linux/rockchip/patches-5.10/104-rockchip-use-USB-host-by-default-on-rk3399-rock-pi-4.patch [deleted file]
target/linux/rockchip/patches-5.10/105-nanopi-r4s-sd-signalling.patch [deleted file]
target/linux/rockchip/patches-5.10/106-arm64-rockchip-add-OF-node-for-pcie-eth-on-NanoPi-R4S.patch [deleted file]
target/linux/rockchip/patches-5.10/107-mmc-core-set-initial-signal-voltage-on-power-off.patch [deleted file]
target/linux/rockchip/patches-5.10/201-rockchip-rk3328-add-i2c0-controller-for-nanopi-r2s.patch [deleted file]
target/linux/rockchip/patches-5.10/202-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus.patch [deleted file]
target/linux/rockchip/patches-5.10/203-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch [deleted file]
target/linux/rockchip/patches-5.10/204-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus-LTS.patch [deleted file]
target/linux/rockchip/patches-5.10/600-net-phy-Add-driver-for-Motorcomm-YT85xx-PHYs.patch [deleted file]
target/linux/rockchip/patches-5.10/801-char-add-support-for-rockchip-hardware-random-number.patch [deleted file]
target/linux/rockchip/patches-5.10/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch [deleted file]
target/linux/rockchip/patches-5.10/803-PM-devfreq-rockchip-add-devfreq-driver-for-rk3328-dmc.patch [deleted file]
target/linux/rockchip/patches-5.10/804-clk-rockchip-support-setting-ddr-clock-via-SIP-Version-2-.patch [deleted file]
target/linux/rockchip/patches-5.10/805-PM-devfreq-rockchip-dfi-add-more-soc-support.patch [deleted file]
target/linux/rockchip/patches-5.10/806-arm64-dts-rockchip-rk3328-add-dfi-node.patch [deleted file]
target/linux/rockchip/patches-5.10/807-arm64-dts-nanopi-r2s-add-rk3328-dmc-relate-node.patch [deleted file]
target/linux/rockchip/patches-5.10/911-kernel-dma-adjust-default-coherent_pool-to-2MiB.patch [deleted file]
target/linux/rockchip/patches-5.10/991-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch [deleted file]
target/linux/rockchip/patches-5.10/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz.patch [deleted file]

index 65cd2ff..40d4fd9 100644 (file)
@@ -8,7 +8,6 @@ FEATURES:=ext4 audio usb usbgadget display gpio fpu pci pcie rootfs-part boot-pa
 SUBTARGETS:=armv8
 
 KERNEL_PATCHVER=5.15
-KERNEL_TESTING_PATCHVER:=5.15
 
 define Target/Description
        Build firmware image for Rockchip SoC devices.
diff --git a/target/linux/rockchip/armv8/config-5.10 b/target/linux/rockchip/armv8/config-5.10
deleted file mode 100644 (file)
index f4d7072..0000000
+++ /dev/null
@@ -1,663 +0,0 @@
-CONFIG_64BIT=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=33
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_ROCKCHIP=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_DEFAULT=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARC_EMAC_CORE=y
-CONFIG_ARM64=y
-CONFIG_ARM64_4K_PAGES=y
-CONFIG_ARM64_CNP=y
-CONFIG_ARM64_CRYPTO=y
-CONFIG_ARM64_ERRATUM_819472=y
-CONFIG_ARM64_ERRATUM_824069=y
-CONFIG_ARM64_ERRATUM_826319=y
-CONFIG_ARM64_ERRATUM_827319=y
-CONFIG_ARM64_ERRATUM_832075=y
-CONFIG_ARM64_ERRATUM_843419=y
-CONFIG_ARM64_ERRATUM_845719=y
-CONFIG_ARM64_ERRATUM_858921=y
-CONFIG_ARM64_HW_AFDBM=y
-CONFIG_ARM64_MODULE_PLTS=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PAN=y
-CONFIG_ARM64_PA_BITS=48
-CONFIG_ARM64_PA_BITS_48=y
-CONFIG_ARM64_PTR_AUTH=y
-CONFIG_ARM64_RAS_EXTN=y
-CONFIG_ARM64_SVE=y
-# CONFIG_ARM64_SW_TTBR0_PAN is not set
-CONFIG_ARM64_TAGGED_ADDR_ABI=y
-CONFIG_ARM64_UAO=y
-CONFIG_ARM64_VA_BITS=48
-# CONFIG_ARM64_VA_BITS_39 is not set
-CONFIG_ARM64_VA_BITS_48=y
-CONFIG_ARM64_VHE=y
-CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
-# CONFIG_ARMV8_DEPRECATED is not set
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
-CONFIG_ARM_CPUIDLE=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GIC_V2M=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_ARM_GIC_V3_ITS_PCI=y
-CONFIG_ARM_MHU=y
-CONFIG_ARM_PSCI_CPUIDLE=y
-CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
-CONFIG_ARM_PSCI_FW=y
-CONFIG_ARM_RK3328_DMC_DEVFREQ=y
-# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set
-# CONFIG_ARM_SCMI_PROTOCOL is not set
-CONFIG_ARM_SCPI_CPUFREQ=y
-CONFIG_ARM_SCPI_POWER_DOMAIN=y
-CONFIG_ARM_SCPI_PROTOCOL=y
-CONFIG_ARM_SMMU=y
-CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
-# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
-CONFIG_ARM_SMMU_V3=y
-# CONFIG_ARM_SMMU_V3_SVA is not set
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_GPIO=y
-CONFIG_BACKLIGHT_PWM=y
-CONFIG_BLK_DEV_BSG=y
-CONFIG_BLK_DEV_BSGLIB=y
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_BLK_DEV_INTEGRITY=y
-CONFIG_BLK_DEV_INTEGRITY_T10=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NVME=y
-CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_PM=y
-CONFIG_BLK_SCSI_REQUEST=y
-CONFIG_BLOCK_COMPAT=y
-CONFIG_BRCMSTB_GISB_ARB=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-# CONFIG_CHARGER_BQ25980 is not set
-CONFIG_CHARGER_GPIO=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLK_PX30=y
-CONFIG_CLK_RK3036=y
-CONFIG_CLK_RK312X=y
-CONFIG_CLK_RK3188=y
-CONFIG_CLK_RK322X=y
-CONFIG_CLK_RK3308=y
-CONFIG_CLK_RK3328=y
-CONFIG_CLK_RK3368=y
-CONFIG_CLK_RK3399=y
-CONFIG_CLK_RV110X=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMA=y
-CONFIG_CMA_ALIGNMENT=8
-CONFIG_CMA_AREAS=7
-# CONFIG_CMA_DEBUG is not set
-# CONFIG_CMA_DEBUGFS is not set
-CONFIG_CMA_SIZE_MBYTES=5
-# CONFIG_CMA_SIZE_SEL_MAX is not set
-CONFIG_CMA_SIZE_SEL_MBYTES=y
-# CONFIG_CMA_SIZE_SEL_MIN is not set
-# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_RK808=y
-CONFIG_COMMON_CLK_ROCKCHIP=y
-CONFIG_COMMON_CLK_SCPI=y
-CONFIG_COMPAT=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_COMPAT_BINFMT_ELF=y
-CONFIG_COMPAT_NETLINK_MESSAGES=y
-CONFIG_COMPAT_OLD_SIGACTION=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_CONTIG_ALLOC=y
-CONFIG_CPUFREQ_DT=y
-CONFIG_CPUFREQ_DT_PLATDEV=y
-CONFIG_CPU_FREQ=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
-CONFIG_CPU_ISOLATION=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CRASH_CORE=y
-CONFIG_CRASH_DUMP=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CRC_T10DIF=y
-CONFIG_CROSS_MEMORY_ATTACH=y
-CONFIG_CRYPTO_AES_ARM64=y
-CONFIG_CRYPTO_AES_ARM64_CE=y
-CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
-CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CRCT10DIF=y
-CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
-CONFIG_CRYPTO_CRYPTD=y
-# CONFIG_CRYPTO_DEV_ROCKCHIP is not set
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_GHASH_ARM64_CE=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_SIMD=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_BUGVERBOSE=y
-# CONFIG_DEVFREQ_GOV_PASSIVE is not set
-CONFIG_DEVFREQ_GOV_PERFORMANCE=y
-CONFIG_DEVFREQ_GOV_POWERSAVE=y
-CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
-CONFIG_DEVFREQ_GOV_USERSPACE=y
-# CONFIG_DEVFREQ_THERMAL is not set
-CONFIG_DEVMEM=y
-# CONFIG_DEVPORT is not set
-CONFIG_DMADEVICES=y
-CONFIG_DMA_CMA=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_REMAP=y
-CONFIG_DMA_SHARED_BUFFER=y
-CONFIG_DNOTIFY=y
-# CONFIG_DRM_ROCKCHIP is not set
-CONFIG_DTC=y
-CONFIG_DT_IDLE_STATES=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_DWMAC_DWC_QOS_ETH=y
-CONFIG_DWMAC_GENERIC=y
-CONFIG_DWMAC_ROCKCHIP=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EEPROM_AT24=y
-CONFIG_EMAC_ROCKCHIP=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_ENERGY_MODEL=y
-CONFIG_EXT4_FS=y
-CONFIG_EXT4_FS_POSIX_ACL=y
-CONFIG_EXTCON=y
-CONFIG_F2FS_FS=y
-CONFIG_FANOTIFY=y
-CONFIG_FHANDLE=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-# CONFIG_FLATMEM_MANUAL is not set
-# CONFIG_FORTIFY_SOURCE is not set
-CONFIG_FRAME_POINTER=y
-CONFIG_FRAME_WARN=2048
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_DWAPB=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-# CONFIG_HARDENED_USERCOPY is not set
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HID=y
-CONFIG_HID_GENERIC=y
-# CONFIG_HISI_HIKEY_USB is not set
-CONFIG_HOLES_IN_ZONE=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HOTPLUG_PCI=y
-# CONFIG_HOTPLUG_PCI_CPCI is not set
-# CONFIG_HOTPLUG_PCI_PCIE is not set
-# CONFIG_HOTPLUG_PCI_SHPC is not set
-CONFIG_HUGETLBFS=y
-CONFIG_HUGETLB_PAGE=y
-CONFIG_HWMON=y
-CONFIG_HWSPINLOCK=y
-CONFIG_HW_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_ROCKCHIP=y
-CONFIG_HZ=250
-CONFIG_HZ_250=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_HELPER_AUTO=y
-CONFIG_I2C_RK3X=y
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_INDIRECT_PIO=y
-CONFIG_INPUT=y
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_FF_MEMLESS=y
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_INPUT_LEDS=y
-CONFIG_INPUT_MATRIXKMAP=y
-# CONFIG_INPUT_MISC is not set
-# CONFIG_INPUT_RK805_PWRKEY is not set
-CONFIG_IOMMU_API=y
-# CONFIG_IOMMU_DEBUGFS is not set
-# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
-CONFIG_IOMMU_DMA=y
-CONFIG_IOMMU_IOVA=y
-CONFIG_IOMMU_IO_PGTABLE=y
-# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
-CONFIG_IOMMU_IO_PGTABLE_LPAE=y
-# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
-CONFIG_IOMMU_SUPPORT=y
-# CONFIG_IO_STRICT_DEVMEM is not set
-CONFIG_IO_URING=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_MSI_IOMMU=y
-CONFIG_IRQ_TIME_ACCOUNTING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_JFFS2_ZLIB=y
-CONFIG_JUMP_LABEL=y
-CONFIG_KALLSYMS=y
-CONFIG_KEXEC_CORE=y
-CONFIG_KEXEC_FILE=y
-CONFIG_KSM=y
-# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
-CONFIG_LEDS_GPIO=y
-# CONFIG_LEDS_LP50XX is not set
-CONFIG_LEDS_PWM=y
-CONFIG_LEDS_SYSCON=y
-CONFIG_LEDS_TRIGGER_CPU=y
-CONFIG_LEDS_TRIGGER_PANIC=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=16
-CONFIG_LIBCRC32C=y
-CONFIG_LIBFDT=y
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MAGIC_SYSRQ_SERIAL=y
-CONFIG_MAILBOX=y
-# CONFIG_MAILBOX_TEST is not set
-CONFIG_MANDATORY_FILE_LOCKING=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_BUS_MUX=y
-CONFIG_MDIO_BUS_MUX_GPIO=y
-CONFIG_MDIO_BUS_MUX_MMIOREG=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MEMORY_ISOLATION=y
-CONFIG_MFD_CORE=y
-# CONFIG_MFD_KHADAS_MCU is not set
-CONFIG_MFD_RK808=y
-# CONFIG_MFD_ROHM_BD71828 is not set
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_BLOCK_MINORS=32
-CONFIG_MMC_CQHCI=y
-CONFIG_MMC_DW=y
-# CONFIG_MMC_DW_BLUEFIELD is not set
-# CONFIG_MMC_DW_EXYNOS is not set
-# CONFIG_MMC_DW_HI3798CV200 is not set
-# CONFIG_MMC_DW_K3 is not set
-# CONFIG_MMC_DW_PCI is not set
-CONFIG_MMC_DW_PLTFM=y
-CONFIG_MMC_DW_ROCKCHIP=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_OF_ARASAN=y
-CONFIG_MMC_SDHCI_OF_DWCMSHC=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MOTORCOMM_PHY=y
-CONFIG_MQ_IOSCHED_DEADLINE=y
-# CONFIG_MTD_CFI is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NLS=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NOP_USB_XCEIV=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=256
-CONFIG_NVMEM=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_NVME_CORE=y
-# CONFIG_NVME_HWMON is not set
-# CONFIG_NVME_MULTIPATH is not set
-# CONFIG_NVME_TCP is not set
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DYNAMIC=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IOMMU=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_NET=y
-CONFIG_OF_OVERLAY=y
-CONFIG_OF_RESOLVE=y
-CONFIG_OLD_SIGSUSPEND3=y
-# CONFIG_OVERLAY_FS_XINO_AUTO is not set
-CONFIG_PADATA=y
-CONFIG_PAGE_POOL=y
-# CONFIG_PANIC_ON_OOPS is not set
-CONFIG_PANIC_ON_OOPS_VALUE=0
-CONFIG_PANIC_TIMEOUT=0
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_PARTITION_PERCPU=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEASPM=y
-CONFIG_PCIEASPM_DEFAULT=y
-# CONFIG_PCIEASPM_PERFORMANCE is not set
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_PME=y
-CONFIG_PCIE_ROCKCHIP=y
-CONFIG_PCIE_ROCKCHIP_HOST=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCI_STUB=y
-CONFIG_PCS_XPCS=y
-CONFIG_PGTABLE_LEVELS=4
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PHY_ROCKCHIP_DP=y
-# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set
-CONFIG_PHY_ROCKCHIP_EMMC=y
-# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set
-# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
-CONFIG_PHY_ROCKCHIP_INNO_USB2=y
-CONFIG_PHY_ROCKCHIP_PCIE=y
-CONFIG_PHY_ROCKCHIP_TYPEC=y
-CONFIG_PHY_ROCKCHIP_USB=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_RK805 is not set
-CONFIG_PINCTRL_ROCKCHIP=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PL330_DMA=y
-CONFIG_PLATFORM_MHU=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_DEVFREQ=y
-# CONFIG_PM_DEVFREQ_EVENT is not set
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_PM_OPP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_POWER_SUPPLY_HWMON=y
-CONFIG_PREEMPT=y
-CONFIG_PREEMPTION=y
-CONFIG_PREEMPT_COUNT=y
-# CONFIG_PREEMPT_NONE is not set
-CONFIG_PREEMPT_RCU=y
-CONFIG_PRINTK_TIME=y
-# CONFIG_PRINT_QUOTA_WARNING is not set
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_PROC_VMCORE=y
-CONFIG_PWM=y
-CONFIG_PWM_ROCKCHIP=y
-CONFIG_PWM_SYSFS=y
-# CONFIG_QFMT_V1 is not set
-# CONFIG_QFMT_V2 is not set
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_QUOTA=y
-CONFIG_QUOTACTL=y
-# CONFIG_QUOTA_NETLINK_INTERFACE is not set
-CONFIG_RAID_ATTRS=y
-CONFIG_RANDOMIZE_BASE=y
-CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-# CONFIG_RAVE_SP_CORE is not set
-CONFIG_RCU_TRACE=y
-CONFIG_REALTEK_PHY=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_IRQ=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FAN53555=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_GPIO=y
-CONFIG_REGULATOR_PWM=y
-CONFIG_REGULATOR_RK808=y
-# CONFIG_REGULATOR_RT4801 is not set
-# CONFIG_REGULATOR_RTMV20 is not set
-CONFIG_RELOCATABLE=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RFS_ACCEL=y
-CONFIG_ROCKCHIP_EFUSE=y
-CONFIG_ROCKCHIP_GRF=y
-CONFIG_ROCKCHIP_IODOMAIN=y
-CONFIG_ROCKCHIP_IOMMU=y
-CONFIG_ROCKCHIP_MBOX=y
-# CONFIG_ROCKCHIP_OTP is not set
-CONFIG_ROCKCHIP_PHY=y
-CONFIG_ROCKCHIP_PM_DOMAINS=y
-CONFIG_ROCKCHIP_THERMAL=y
-CONFIG_ROCKCHIP_TIMER=y
-CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
-CONFIG_RPS=y
-CONFIG_RSEQ=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_RK808=y
-# CONFIG_RTC_DRV_RV3032 is not set
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_NVMEM=y
-# CONFIG_RUNTIME_TESTING_MENU is not set
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SCHED_MC=y
-CONFIG_SCSI=y
-# CONFIG_SCSI_LOWLEVEL is not set
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_SCSI_SAS_ATTRS=y
-CONFIG_SCSI_SAS_HOST_SMP=y
-CONFIG_SCSI_SAS_LIBSAS=y
-# CONFIG_SECURITY_DMESG_RESTRICT is not set
-CONFIG_SENSORS_ARM_SCPI=y
-# CONFIG_SENSORS_MR75203 is not set
-CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
-CONFIG_SERIAL_8250_DW=y
-CONFIG_SERIAL_8250_DWLIB=y
-CONFIG_SERIAL_8250_EXAR=y
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-CONFIG_SERIAL_DEV_BUS=y
-CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIO=y
-CONFIG_SERIO_AMBAKMI=y
-CONFIG_SERIO_LIBPS2=y
-CONFIG_SG_POOL=y
-CONFIG_SIMPLE_PM_BUS=y
-CONFIG_SLUB_DEBUG=y
-CONFIG_SMP=y
-# CONFIG_SND_SOC_ROCKCHIP is not set
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_MANUAL=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_DYNAMIC=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_ROCKCHIP=y
-CONFIG_SPI_SPIDEV=y
-# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
-CONFIG_SQUASHFS_DECOMP_SINGLE=y
-# CONFIG_SQUASHFS_EMBEDDED is not set
-CONFIG_SQUASHFS_FILE_CACHE=y
-# CONFIG_SQUASHFS_FILE_DIRECT is not set
-CONFIG_SRAM=y
-CONFIG_SRCU=y
-CONFIG_STACKPROTECTOR=y
-CONFIG_STACKPROTECTOR_STRONG=y
-CONFIG_STMMAC_ETH=y
-CONFIG_STMMAC_PLATFORM=y
-# CONFIG_STMMAC_SELFTESTS is not set
-CONFIG_STRICT_DEVMEM=y
-# CONFIG_STRIP_ASM_SYMS is not set
-# CONFIG_SWAP is not set
-CONFIG_SWIOTLB=y
-CONFIG_SWPHY=y
-CONFIG_SYNC_FILE=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYSFS_SYSCALL=y
-CONFIG_SYSVIPC_COMPAT=y
-CONFIG_SYS_SUPPORTS_HUGETLBFS=y
-# CONFIG_TEXTSEARCH is not set
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_EMULATION=y
-CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_OF=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TRACE_CLOCK=y
-CONFIG_TRANSPARENT_HUGEPAGE=y
-CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
-# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_TYPEC=y
-# CONFIG_TYPEC_DP_ALTMODE is not set
-CONFIG_TYPEC_FUSB302=y
-# CONFIG_TYPEC_HD3SS3220 is not set
-# CONFIG_TYPEC_MUX_PI3USB30532 is not set
-# CONFIG_TYPEC_STUSB160X is not set
-# CONFIG_TYPEC_TCPCI is not set
-CONFIG_TYPEC_TCPM=y
-# CONFIG_TYPEC_TPS6598X is not set
-# CONFIG_UACCE is not set
-# CONFIG_UCLAMP_TASK is not set
-# CONFIG_UEVENT_HELPER is not set
-CONFIG_UNINLINE_SPIN_UNLOCK=y
-CONFIG_UNMAP_KERNEL_AT_EL0=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_HOST=y
-CONFIG_USB_DWC3_OF_SIMPLE=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_HCD_PLATFORM=y
-# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
-CONFIG_USB_HID=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_HCD_PLATFORM=y
-CONFIG_USB_PHY=y
-CONFIG_USB_ROLE_SWITCH=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ULPI=y
-CONFIG_USB_ULPI_BUS=y
-CONFIG_USB_ULPI_VIEWPORT=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_PLATFORM=y
-# CONFIG_VIRTIO_MENU is not set
-CONFIG_VMAP_STACK=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-# CONFIG_WATCHDOG is not set
-CONFIG_XARRAY_MULTI=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_ARMTHUMB=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZONE_DMA32=y
index cc5b4b0..475a53e 100644 (file)
@@ -19,9 +19,6 @@
  *             Automotive 100/10 hyper range Phys: yt8510
  */
 
-#include <linux/iversion.h>
-#include <linux/version.h>
-
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/phy.h>
@@ -312,20 +309,13 @@ static int yt8521_config_intr(struct phy_device *phydev)
        return phy_write(phydev, REG_INT_MASK, val);
 }
 
-#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0)
-static int yt8521_ack_interrupt(struct phy_device *phydev)
-#else
 static irqreturn_t yt8521_ack_interrupt(struct phy_device *phydev)
-#endif
 {
        int val;
 
        val = phy_read(phydev, REG_INT_STATUS);
        phydev_dbg(phydev, "intr status 0x04%x\n", val);
 
-#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0)
-       return (val < 0) ? val : 0;
-#else
        if (val < 0) {
                phy_error(phydev);
                return IRQ_NONE;
@@ -333,7 +323,6 @@ static irqreturn_t yt8521_ack_interrupt(struct phy_device *phydev)
 
        phy_trigger_machine(phydev);
        return IRQ_HANDLED;
-#endif
 }
 
 static struct phy_driver ytphy_drvs[] = {
@@ -382,11 +371,7 @@ static struct phy_driver ytphy_drvs[] = {
                .phy_id_mask    = MOTORCOMM_PHY_ID_MASK,
                /* PHY_GBIT_FEATURES */
                .config_init    = yt8521_config_init,
-#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0)
-               .ack_interrupt  = yt8521_ack_interrupt,
-#else
                .handle_interrupt = yt8521_ack_interrupt,
-#endif
                .config_intr    = yt8521_config_intr,
                .suspend        = genphy_suspend,
                .resume         = genphy_resume,
@@ -397,11 +382,7 @@ static struct phy_driver ytphy_drvs[] = {
                .phy_id_mask    = MOTORCOMM_PHY_ID_MASK,
                /* PHY_GBIT_FEATURES */
                .config_init    = yt8521_config_init,
-#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0)
-               .ack_interrupt  = yt8521_ack_interrupt,
-#else
                .handle_interrupt = yt8521_ack_interrupt,
-#endif
                .config_intr    = yt8521_config_intr,
                .suspend        = genphy_suspend,
                .resume         = genphy_resume,
index eda83a2..a152e31 100644 (file)
@@ -24,7 +24,7 @@ define KernelPackage/drm-rockchip
        CONFIG_ROCKCHIP_LVDS=y \
        CONFIG_ROCKCHIP_RGB=n \
        CONFIG_ROCKCHIP_RK3066_HDMI=n \
-       CONFIG_DRM_DP_AUX_BUS@ge5.15 \
+       CONFIG_DRM_DP_AUX_BUS \
        CONFIG_DRM_PANEL=y \
        CONFIG_DRM_PANEL_BRIDGE=y \
        CONFIG_DRM_PANEL_SIMPLE
@@ -34,7 +34,7 @@ define KernelPackage/drm-rockchip
        $(LINUX_DIR)/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.ko \
        $(LINUX_DIR)/drivers/media/cec/core/cec.ko \
        $(LINUX_DIR)/drivers/phy/rockchip/phy-rockchip-inno-hdmi.ko \
-       $(LINUX_DIR)/drivers/gpu/drm/drm_dp_aux_bus.ko@ge5.15 \
+       $(LINUX_DIR)/drivers/gpu/drm/drm_dp_aux_bus.ko \
        $(LINUX_DIR)/drivers/gpu/drm/panel/panel-simple.ko \
        $(LINUX_DIR)/drivers/gpu/drm/rockchip/rockchipdrm.ko
   AUTOLOAD:=$(call AutoProbe,rockchipdrm phy-rockchip-inno-hdmi dw-hdmi-cec)
diff --git a/target/linux/rockchip/patches-5.10/005-rockchip-rk3328-add-compatible-to-NanoPi-R2S-etherne.patch b/target/linux/rockchip/patches-5.10/005-rockchip-rk3328-add-compatible-to-NanoPi-R2S-etherne.patch
deleted file mode 100644 (file)
index 085dd39..0000000
+++ /dev/null
@@ -1,25 +0,0 @@
-From bc6c96d850419e71dbc9b0094ccc9b668ba9be43 Mon Sep 17 00:00:00 2001
-From: David Bauer <mail@david-bauer.net>
-Date: Mon, 28 Sep 2020 22:54:52 +0200
-Subject: [PATCH] rockchip: rk3328: add compatible to NanoPi R2S ethernet PHY
-
-This adds the compatible property to the NanoPi R2S ethernet PHY node.
-Otherwise, the PHY might not be probed, as the PHY ID reads all 0xff
-when it is still in reset.
-
-Signed-off-by: David Bauer <mail@david-bauer.net>
----
- arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
-@@ -138,6 +138,8 @@
-               #size-cells = <0>;
-               rtl8211e: ethernet-phy@1 {
-+                      compatible = "ethernet-phy-id001c.c915",
-+                                   "ethernet-phy-ieee802.3-c22";
-                       reg = <1>;
-                       pinctrl-0 = <&eth_phy_reset_pin>;
-                       pinctrl-names = "default";
diff --git a/target/linux/rockchip/patches-5.10/006-v5.13-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch b/target/linux/rockchip/patches-5.10/006-v5.13-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch
deleted file mode 100644 (file)
index 461a5ae..0000000
+++ /dev/null
@@ -1,177 +0,0 @@
-From db792e9adbf85ffc9d6b0b060ac3c8e3148c8992 Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Fri, 19 Mar 2021 13:16:27 +0800
-Subject: [PATCH] rockchip: rk3399: Add support for FriendlyARM NanoPi R4S
-
-This adds support for the NanoPi R4S from FriendlyArm.
-
-Rockchip RK3399 SoC
-1GB DDR3 or 4GB LPDDR4 RAM
-Gigabit Ethernet (WAN)
-Gigabit Ethernet (PCIe) (LAN)
-USB 3.0 Port x 2
-MicroSD slot
-Reset button
-WAN - LAN - SYS LED
-
-Co-developed-by: Jensen Huang <jensenhuang@friendlyarm.com>
-Signed-off-by: Jensen Huang <jensenhuang@friendlyarm.com>
-[minor adjustments]
-Co-developed-by: Marty Jones <mj8263788@gmail.com>
-Signed-off-by: Marty Jones <mj8263788@gmail.com>
-[further adjustments, fixed format issues]
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
-Link: https://lore.kernel.org/r/20210319051627.814-2-cnsztl@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/Makefile         |   1 +
- .../boot/dts/rockchip/rk3399-nanopi-r4s.dts   | 133 +++++++++++++++++++++
- 2 files changed, 134 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
-
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -30,6 +30,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-le
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-neo4.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-orangepi.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinebook-pro.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
-@@ -0,0 +1,133 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * FriendlyElec NanoPC-T4 board device tree source
-+ *
-+ * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd.
-+ * (http://www.friendlyarm.com)
-+ *
-+ * Copyright (c) 2018 Collabora Ltd.
-+ *
-+ * Copyright (c) 2020 Jensen Huang <jensenhuang@friendlyarm.com>
-+ * Copyright (c) 2020 Marty Jones <mj8263788@gmail.com>
-+ * Copyright (c) 2021 Tianling Shen <cnsztl@gmail.com>
-+ */
-+
-+/dts-v1/;
-+#include "rk3399-nanopi4.dtsi"
-+
-+/ {
-+      model = "FriendlyElec NanoPi R4S";
-+      compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399";
-+
-+      /delete-node/ display-subsystem;
-+
-+      gpio-leds {
-+              pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
-+
-+              /delete-node/ led-0;
-+
-+              lan_led: led-lan {
-+                      gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
-+                      label = "green:lan";
-+              };
-+
-+              sys_led: led-sys {
-+                      gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
-+                      label = "red:sys";
-+                      default-state = "on";
-+              };
-+
-+              wan_led: led-wan {
-+                      gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
-+                      label = "green:wan";
-+              };
-+      };
-+
-+      gpio-keys {
-+              pinctrl-0 = <&reset_button_pin>;
-+
-+              /delete-node/ power;
-+
-+              reset {
-+                      debounce-interval = <50>;
-+                      gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
-+                      label = "reset";
-+                      linux,code = <KEY_RESTART>;
-+              };
-+      };
-+
-+      vdd_5v: vdd-5v {
-+              compatible = "regulator-fixed";
-+              regulator-name = "vdd_5v";
-+              regulator-always-on;
-+              regulator-boot-on;
-+      };
-+};
-+
-+&emmc_phy {
-+      status = "disabled";
-+};
-+
-+&i2c4 {
-+      status = "disabled";
-+};
-+
-+&pcie0 {
-+      max-link-speed = <1>;
-+      num-lanes = <1>;
-+      vpcie3v3-supply = <&vcc3v3_sys>;
-+};
-+
-+&pinctrl {
-+      gpio-leds {
-+              /delete-node/ status-led-pin;
-+
-+              lan_led_pin: lan-led-pin {
-+                      rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
-+              };
-+
-+              sys_led_pin: sys-led-pin {
-+                      rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
-+              };
-+
-+              wan_led_pin: wan-led-pin {
-+                      rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
-+              };
-+      };
-+
-+      rockchip-key {
-+              /delete-node/ power-key;
-+
-+              reset_button_pin: reset-button-pin {
-+                      rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
-+              };
-+      };
-+};
-+
-+&sdhci {
-+      status = "disabled";
-+};
-+
-+&sdio0 {
-+      status = "disabled";
-+};
-+
-+&u2phy0_host {
-+      phy-supply = <&vdd_5v>;
-+};
-+
-+&u2phy1_host {
-+      status = "disabled";
-+};
-+
-+&uart0 {
-+      status = "disabled";
-+};
-+
-+&usbdrd_dwc3_0 {
-+      dr_mode = "host";
-+};
-+
-+&vcc3v3_sys {
-+      vin-supply = <&vcc5v0_sys>;
-+};
diff --git a/target/linux/rockchip/patches-5.10/007-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch b/target/linux/rockchip/patches-5.10/007-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch
deleted file mode 100644 (file)
index cd6640f..0000000
+++ /dev/null
@@ -1,40 +0,0 @@
-From 43f3999d1836117ab2e601aec9a9e6f292ce4958 Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Mon, 7 Jun 2021 15:45:37 +0800
-Subject: [PATCH] arm64: dts: rockchip: add EEPROM node for NanoPi R4S
-
-NanoPi R4S has a EEPROM attached to the 2nd I2C bus (U92), which
-stores the MAC address.
-
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
----
- .../boot/dts/rockchip/rk3399-nanopi-r4s.dts    | 18 ++++++++++++++++++
- 1 file changed, 18 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
-@@ -68,6 +68,24 @@
-       status = "disabled";
- };
-+&gmac {
-+      nvmem-cells = <&mac_address>;
-+      nvmem-cell-names = "mac-address";
-+};
-+
-+&i2c2 {
-+      eeprom@51 {
-+              compatible = "microchip,24c02", "atmel,24c02";
-+              reg = <0x51>;
-+              pagesize = <16>;
-+              size = <256>;
-+
-+              mac_address: mac-address@fa {
-+                      reg = <0xfa 0x06>;
-+              };
-+      };
-+};
-+
- &i2c4 {
-       status = "disabled";
- };
diff --git a/target/linux/rockchip/patches-5.10/100-rockchip-use-system-LED-for-OpenWrt.patch b/target/linux/rockchip/patches-5.10/100-rockchip-use-system-LED-for-OpenWrt.patch
deleted file mode 100644 (file)
index d0860de..0000000
+++ /dev/null
@@ -1,47 +0,0 @@
-From 6731d2c9039fbe1ecf21915eab3acee0a999508a Mon Sep 17 00:00:00 2001
-From: David Bauer <mail@david-bauer.net>
-Date: Fri, 10 Jul 2020 21:38:20 +0200
-Subject: [PATCH] rockchip: use system LED for OpenWrt
-
-Use the SYS LED on the casing for showing system status.
-
-This patch is kept separate from the NanoPi R2S support patch, as i plan
-on submitting the device support upstream.
-
-Signed-off-by: David Bauer <mail@david-bauer.net>
----
- arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 9 ++++++++-
- 1 file changed, 8 insertions(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
-@@ -13,6 +13,13 @@
-       model = "FriendlyElec NanoPi R2S";
-       compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328";
-+      aliases {
-+              led-boot = &sys_led;
-+              led-failsafe = &sys_led;
-+              led-running = &sys_led;
-+              led-upgrade = &sys_led;
-+      };
-+
-       chosen {
-               stdout-path = "serial2:1500000n8";
-       };
---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
-@@ -19,6 +19,13 @@
-       model = "FriendlyElec NanoPi R4S";
-       compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399";
-+      aliases {
-+              led-boot = &sys_led;
-+              led-failsafe = &sys_led;
-+              led-running = &sys_led;
-+              led-upgrade = &sys_led;
-+      };
-+
-       /delete-node/ display-subsystem;
-       gpio-leds {
diff --git a/target/linux/rockchip/patches-5.10/101-dts-rockchip-add-usb3-controller-node-for-RK3328-SoCs.patch b/target/linux/rockchip/patches-5.10/101-dts-rockchip-add-usb3-controller-node-for-RK3328-SoCs.patch
deleted file mode 100644 (file)
index 2dd6e40..0000000
+++ /dev/null
@@ -1,70 +0,0 @@
-From: William Wu <william.wu@rock-chips.com>
-
-RK3328 has one USB 3.0 OTG controller which uses DWC_USB3
-core's general architecture. It can act as static xHCI host
-controller, static device controller, USB 3.0/2.0 OTG basing
-on ID of USB3.0 PHY.
-
-Signed-off-by: William Wu <william.wu@rock-chips.com>
-Signed-off-by: Leonidas P. Papadakos <papadakospan@gmail.com>
-
----
-
-NOTE: This binding still has issues. From the original thread:
-
-the rk3328 usb3-phy has an issue with detecting any plugin events
-after a previous device got removed - see the inno-usb3-phy driver
-in the vendor kernel.
-
-The current state is good-enough for enabling the USB3 attached LAN
-port of the NanoPi R2S. However, it might explode depending on your
-use-case. You've been warned.
-
----
- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 27 ++++++++++++++++++++++++
- 1 file changed, 27 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
-@@ -985,22 +985,30 @@
-       };
-       usbdrd3: usb@ff600000 {
--              compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
--              reg = <0x0 0xff600000 0x0 0x100000>;
--              interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
-+              compatible = "rockchip,rk3328-dwc3", "rockchip,rk3399-dwc3";
-               clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
-                        <&cru ACLK_USB3OTG>;
-               clock-names = "ref_clk", "suspend_clk",
-                             "bus_clk";
--              dr_mode = "otg";
--              phy_type = "utmi_wide";
--              snps,dis-del-phy-power-chg-quirk;
--              snps,dis_enblslpm_quirk;
--              snps,dis-tx-ipgap-linecheck-quirk;
--              snps,dis-u2-freeclk-exists-quirk;
--              snps,dis_u2_susphy_quirk;
--              snps,dis_u3_susphy_quirk;
-+              #address-cells = <2>;
-+              #size-cells = <2>;
-+              ranges;
-               status = "disabled";
-+
-+              usbdrd_dwc3: dwc3@ff600000 {
-+                      compatible = "snps,dwc3";
-+                      reg = <0x0 0xff600000 0x0 0x100000>;
-+                      interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
-+                      dr_mode = "otg";
-+                      phy_type = "utmi_wide";
-+                      snps,dis_enblslpm_quirk;
-+                      snps,dis-u2-freeclk-exists-quirk;
-+                      snps,dis_u2_susphy_quirk;
-+                      snps,dis_u3_susphy_quirk;
-+                      snps,dis-del-phy-power-chg-quirk;
-+                      snps,dis-tx-ipgap-linecheck-quirk;
-+                      status = "disabled";
-+              };
-       };
-       gic: interrupt-controller@ff811000 {
diff --git a/target/linux/rockchip/patches-5.10/102-rockchip-enable-LAN-port-on-NanoPi-R2S.patch b/target/linux/rockchip/patches-5.10/102-rockchip-enable-LAN-port-on-NanoPi-R2S.patch
deleted file mode 100644 (file)
index e6b1a2f..0000000
+++ /dev/null
@@ -1,60 +0,0 @@
-From 0fc3b9b7619c4878f73a6a7989863f0d1a3fd392 Mon Sep 17 00:00:00 2001
-From: David Bauer <mail@david-bauer.net>
-Date: Fri, 10 Jul 2020 21:12:16 +0200
-Subject: [PATCH] rockchip: enabled LAN port on NanoPi R2S
-
-Enable the USB3 port on the FriendlyARM NanoPi R2S.
-This is required for the USB3 attached LAN port to work.
-
-Signed-off-by: David Bauer <mail@david-bauer.net>
----
- .../boot/dts/rockchip/rk3328-nanopi-r2s.dts   | 27 +++++++++++++++++++
- 1 file changed, 27 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
-@@ -103,6 +103,18 @@
-               regulator-min-microvolt = <5000000>;
-               regulator-max-microvolt = <5000000>;
-       };
-+
-+      vdd_5v_lan: vdd-5v-lan {
-+              compatible = "regulator-fixed";
-+              enable-active-high;
-+              gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
-+              pinctrl-0 = <&lan_vdd_pin>;
-+              pinctrl-names = "default";
-+              regulator-name = "vdd_5v_lan";
-+              regulator-always-on;
-+              regulator-boot-on;
-+              vin-supply = <&vdd_5v>;
-+      };
- };
- &cpu0 {
-@@ -313,6 +325,12 @@
-               };
-       };
-+      lan {
-+              lan_vdd_pin: lan-vdd-pin {
-+                      rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
-+              };
-+      };
-+
-       pmic {
-               pmic_int_l: pmic-int-l {
-                       rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
-@@ -379,3 +397,12 @@
- &usb_host0_ohci {
-       status = "okay";
- };
-+
-+&usbdrd3 {
-+      status = "okay";
-+};
-+
-+&usbdrd_dwc3 {
-+      dr_mode = "host";
-+      status = "okay";
-+};
diff --git a/target/linux/rockchip/patches-5.10/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch b/target/linux/rockchip/patches-5.10/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch
deleted file mode 100644 (file)
index d25460f..0000000
+++ /dev/null
@@ -1,28 +0,0 @@
-From 2795c8b31a686bdb8338f9404d18ef7a154f0d75 Mon Sep 17 00:00:00 2001
-From: David Bauer <mail@david-bauer.net>
-Date: Sun, 26 Jul 2020 13:32:59 +0200
-Subject: [PATCH] arm64: rockchip: add OF node for USB eth on NanoPi R2S
-
-This adds the OF node for the USB3 ethernet adapter on the FriendlyARM
-NanoPi R2S. Add the correct value for the RTL8153 LED configuration
-register to match the blink behavior of the other port on the device.
-
-Signed-off-by: David Bauer <mail@david-bauer.net>
----
- arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
-@@ -405,4 +405,11 @@
- &usbdrd_dwc3 {
-       dr_mode = "host";
-       status = "okay";
-+
-+      usb_eth: usb-eth@2 {
-+              compatible = "realtek,rtl8153";
-+              reg = <2>;
-+
-+              realtek,led-data = <0x87>;
-+      };
- };
diff --git a/target/linux/rockchip/patches-5.10/104-rockchip-use-USB-host-by-default-on-rk3399-rock-pi-4.patch b/target/linux/rockchip/patches-5.10/104-rockchip-use-USB-host-by-default-on-rk3399-rock-pi-4.patch
deleted file mode 100644 (file)
index da87227..0000000
+++ /dev/null
@@ -1,32 +0,0 @@
-From e12f67fe83446432ef16704c22ec23bd1dbcd094 Mon Sep 17 00:00:00 2001
-From: Vicente Bergas <vicencb@gmail.com>
-Date: Tue, 1 Dec 2020 16:41:32 +0100
-Subject: arm64: dts: rockchip: use USB host by default on rk3399-rock-pi-4
-
-Based on the board schematics at
-https://dl.radxa.com/rockpi4/docs/hw/rockpi4/rockpi_4c_v12_sch_20200620.pdf
-on page 19 there is an USB Type-A receptacle being used as an USB-OTG port.
-
-But the Type-A connector is not valid for OTG operation, for this reason
-there is a switch to select host or device role.
-This is non-compliant and error prone because switching is manual.
-So, use host mode as it corresponds for a Type-A receptacle.
-
-Signed-off-by: Vicente Bergas <vicencb@gmail.com>
-Link: https://lore.kernel.org/r/20201201154132.1286-4-vicencb@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
-@@ -680,7 +680,7 @@
- &usbdrd_dwc3_0 {
-       status = "okay";
--      dr_mode = "otg";
-+      dr_mode = "host";
- };
- &usbdrd3_1 {
diff --git a/target/linux/rockchip/patches-5.10/105-nanopi-r4s-sd-signalling.patch b/target/linux/rockchip/patches-5.10/105-nanopi-r4s-sd-signalling.patch
deleted file mode 100644 (file)
index a04c14b..0000000
+++ /dev/null
@@ -1,26 +0,0 @@
-From: David Bauer <mail@david-bauer.net>
-Subject: arm64: dts: rockchip: disable UHS modes for NanoPi R4S
-
-The NanoPi R4S leaves the SD card in 1.8V signalling when rebooting
-while U-Boot requires the card to be in 3.3V mode.
-
-Remove UHS support from the SD controller so the card remains in 3.3V
-mode. This reduces transfer speeds but ensures a reboot whether from
-userspace or following a kernel panic is always working.
-
-Signed-off-by: David Bauer <mail@david-bauer.net>
-
---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
-@@ -121,6 +121,11 @@
-       status = "disabled";
- };
-+&sdmmc {
-+      /delete-property/ sd-uhs-sdr104;
-+      cap-sd-highspeed;
-+};
-+
- &u2phy0_host {
-       phy-supply = <&vdd_5v>;
- };
diff --git a/target/linux/rockchip/patches-5.10/106-arm64-rockchip-add-OF-node-for-pcie-eth-on-NanoPi-R4S.patch b/target/linux/rockchip/patches-5.10/106-arm64-rockchip-add-OF-node-for-pcie-eth-on-NanoPi-R4S.patch
deleted file mode 100644 (file)
index d76563e..0000000
+++ /dev/null
@@ -1,22 +0,0 @@
---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
-@@ -101,6 +101,19 @@
-       max-link-speed = <1>;
-       num-lanes = <1>;
-       vpcie3v3-supply = <&vcc3v3_sys>;
-+
-+      pcie@0 {
-+              reg = <0x00000000 0 0 0 0>;
-+              #address-cells = <3>;
-+              #size-cells = <2>;
-+
-+              pcie-eth@0,0 {
-+                      compatible = "pci10ec,8168";
-+                      reg = <0x000000 0 0 0 0>;
-+
-+                      realtek,led-data = <0x870>;
-+              };
-+      };
- };
- &pinctrl {
diff --git a/target/linux/rockchip/patches-5.10/107-mmc-core-set-initial-signal-voltage-on-power-off.patch b/target/linux/rockchip/patches-5.10/107-mmc-core-set-initial-signal-voltage-on-power-off.patch
deleted file mode 100644 (file)
index ef30115..0000000
+++ /dev/null
@@ -1,35 +0,0 @@
-From 0d329112c709d6cfedf0fffb19f0cc6b19043f6b Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Wed, 20 Feb 2019 07:38:34 +0000
-Subject: [PATCH] mmc: core: set initial signal voltage on power off
-
-Some boards have SD card connectors where the power rail cannot be switched
-off by the driver. If the card has not been power cycled, it may still be
-using 1.8V signaling after a warm re-boot. Bootroms expecting 3.3V signaling
-will fail to boot from a UHS card that continue to use 1.8V signaling.
-
-Set initial signal voltage in mmc_power_off() to allow re-boot to function.
-
-This fixes re-boot with UHS cards on Asus Tinker Board (Rockchip RK3288),
-same issue have been seen on some Rockchip RK3399 boards.
-
-I am sending this as a RFC because I have no insights into SD/MMC subsystem,
-this change fix a re-boot issue on my boards and does not break emmc/sdio.
-Is this an acceptable workaround? Any advice is appreciated.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- drivers/mmc/core/core.c | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/mmc/core/core.c
-+++ b/drivers/mmc/core/core.c
-@@ -1354,6 +1354,8 @@ void mmc_power_off(struct mmc_host *host
-       mmc_pwrseq_power_off(host);
-+      mmc_set_initial_signal_voltage(host);
-+
-       host->ios.clock = 0;
-       host->ios.vdd = 0;
diff --git a/target/linux/rockchip/patches-5.10/201-rockchip-rk3328-add-i2c0-controller-for-nanopi-r2s.patch b/target/linux/rockchip/patches-5.10/201-rockchip-rk3328-add-i2c0-controller-for-nanopi-r2s.patch
deleted file mode 100644 (file)
index edf007e..0000000
+++ /dev/null
@@ -1,22 +0,0 @@
-From 3b7eb946b1d640d684a921e53e1e50985ab7eb89 Mon Sep 17 00:00:00 2001
-From: QiuSimons <45143996+QiuSimons@users.noreply.github.com>
-Date: Tue, 4 Aug 2020 20:17:53 +0800
-Subject: [PATCH] rockchip: rk3328: add i2c0 controller for nanopi r2s
-
----
- arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 4 ++++
- 1 files changed, 4 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
-@@ -169,6 +169,10 @@
-       };
- };
-+&i2c0 {
-+      status = "okay";
-+};
-+
- &i2c1 {
-       status = "okay";
diff --git a/target/linux/rockchip/patches-5.10/202-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus.patch b/target/linux/rockchip/patches-5.10/202-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus.patch
deleted file mode 100644 (file)
index 2166676..0000000
+++ /dev/null
@@ -1,52 +0,0 @@
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-od
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
-@@ -0,0 +1,39 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+#include "rk3328-nanopi-r2s.dts"
-+
-+/ {
-+      model = "Xunlong Orange Pi R1 Plus";
-+      compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
-+};
-+
-+&lan_led {
-+      label = "orangepi-r1-plus:green:lan";
-+};
-+
-+&spi0 {
-+      max-freq = <48000000>;
-+      status = "okay";
-+
-+      flash@0 {
-+              compatible = "jedec,spi-nor";
-+              reg = <0>;
-+              spi-max-frequency = <10000000>;
-+      };
-+};
-+
-+&sys_led {
-+      gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
-+      label = "orangepi-r1-plus:red:sys";
-+};
-+
-+&sys_led_pin {
-+      rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
-+};
-+
-+&uart1 {
-+      status = "okay";
-+};
-+
-+&wan_led {
-+      label = "orangepi-r1-plus:green:wan";
-+};
diff --git a/target/linux/rockchip/patches-5.10/203-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch b/target/linux/rockchip/patches-5.10/203-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch
deleted file mode 100644 (file)
index 078efd4..0000000
+++ /dev/null
@@ -1,64 +0,0 @@
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -6,6 +6,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a9
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
-@@ -0,0 +1,51 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
-+ * (http://www.friendlyarm.com)
-+ *
-+ * Copyright (c) 2021 Tianling Shen <cnsztl@immortalwrt.org>
-+ */
-+
-+/dts-v1/;
-+
-+#include "rk3328-nanopi-r2s.dts"
-+
-+/ {
-+      model = "FriendlyElec NanoPi R2C";
-+      compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
-+};
-+
-+&gmac2io {
-+      phy-handle = <&yt8521s>;
-+
-+      mdio {
-+              /delete-node/ ethernet-phy@1;
-+
-+              yt8521s: ethernet-phy@3 {
-+                      compatible = "ethernet-phy-id0000.011a",
-+                                   "ethernet-phy-ieee802.3-c22";
-+                      reg = <3>;
-+                      pinctrl-0 = <&eth_phy_reset_pin>;
-+                      pinctrl-names = "default";
-+                      reset-assert-us = <10000>;
-+                      reset-deassert-us = <50000>;
-+                      reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
-+              };
-+      };
-+};
-+
-+&lan_led {
-+      label = "nanopi-r2c:green:lan";
-+};
-+
-+&sys_led {
-+      label = "nanopi-r2c:red:sys";
-+};
-+
-+&usb_eth {
-+      realtek,led-data = <0x78>;
-+};
-+
-+&wan_led {
-+      label = "nanopi-r2c:green:wan";
-+};
diff --git a/target/linux/rockchip/patches-5.10/204-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus-LTS.patch b/target/linux/rockchip/patches-5.10/204-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus-LTS.patch
deleted file mode 100644 (file)
index 28c3375..0000000
+++ /dev/null
@@ -1,79 +0,0 @@
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-ev
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
-@@ -0,0 +1,66 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (c) 2016 Xunlong Software. Co., Ltd.
-+ * (http://www.orangepi.org)
-+ *
-+ * Copyright (c) 2021 Tianling Shen <cnsztl@immortalwrt.org>
-+ */
-+
-+#include "rk3328-orangepi-r1-plus.dts"
-+
-+/ {
-+      model = "Xunlong Orange Pi R1 Plus LTS";
-+      compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
-+};
-+
-+&dmc_opp_table {
-+      opp-798000000 {
-+              status = "disabled";
-+      };
-+      opp-840000000 {
-+              status = "disabled";
-+      };
-+      opp-924000000 {
-+              status = "disabled";
-+      };
-+      opp-1056000000 {
-+              status = "disabled";
-+      };
-+};
-+
-+&gmac2io {
-+      phy-handle = <&yt8531c>;
-+      tx_delay = <0x19>;
-+      rx_delay = <0x05>;
-+
-+      mdio {
-+              /delete-node/ ethernet-phy@1;
-+
-+              yt8531c: ethernet-phy@0 {
-+                      compatible = "ethernet-phy-id4f51.e91b",
-+                                   "ethernet-phy-ieee802.3-c22";
-+                      reg = <0>;
-+                      pinctrl-0 = <&eth_phy_reset_pin>;
-+                      pinctrl-names = "default";
-+                      reset-assert-us = <15000>;
-+                      reset-deassert-us = <50000>;
-+                      reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
-+              };
-+      };
-+};
-+
-+&lan_led {
-+      label = "orangepi-r1-plus-lts:green:lan";
-+};
-+
-+&sys_led {
-+      label = "orangepi-r1-plus-lts:red:sys";
-+};
-+
-+&usb_eth {
-+      realtek,led-data = <0x78>;
-+};
-+
-+&wan_led {
-+      label = "orangepi-r1-plus-lts:green:wan";
-+};
diff --git a/target/linux/rockchip/patches-5.10/600-net-phy-Add-driver-for-Motorcomm-YT85xx-PHYs.patch b/target/linux/rockchip/patches-5.10/600-net-phy-Add-driver-for-Motorcomm-YT85xx-PHYs.patch
deleted file mode 100644 (file)
index 9ded066..0000000
+++ /dev/null
@@ -1,39 +0,0 @@
-From 5d6862cc5eac1679d7a4ef388f7c9bbc70e76770 Mon Sep 17 00:00:00 2001
-From: hmz007 <hmz007@gmail.com>
-Date: Mon, 5 Jul 2021 17:03:00 +0800
-Subject: [PATCH] net: phy: Add driver for Motorcomm YT85xx PHYs
-
-Signed-off-by: hmz007 <hmz007@gmail.com>
----
- drivers/net/phy/Kconfig       |   5 +
- drivers/net/phy/Makefile      |   1 +
- drivers/net/phy/motorcomm.c   | 346 ++++++++++++++++++++++++++++++++++
- include/linux/motorcomm_phy.h |  68 +++++++
- 4 files changed, 420 insertions(+)
- create mode 100644 drivers/net/phy/motorcomm.c
- create mode 100644 include/linux/motorcomm_phy.h
-
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -297,6 +297,11 @@ config MICROSEMI_PHY
-       help
-         Currently supports VSC8514, VSC8530, VSC8531, VSC8540 and VSC8541 PHYs
-+config MOTORCOMM_PHY
-+      tristate "Motorcomm PHYs"
-+      help
-+        Supports the YT8010, YT8510, YT8511, YT8512 PHYs.
-+
- config NATIONAL_PHY
-       tristate "National Semiconductor PHYs"
-       help
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -82,6 +82,7 @@ obj-$(CONFIG_MICREL_PHY)     += micrel.o
- obj-$(CONFIG_MICROCHIP_PHY)   += microchip.o
- obj-$(CONFIG_MICROCHIP_T1_PHY)        += microchip_t1.o
- obj-$(CONFIG_MICROSEMI_PHY)   += mscc/
-+obj-$(CONFIG_MOTORCOMM_PHY) += motorcomm.o
- obj-$(CONFIG_NATIONAL_PHY)    += national.o
- obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o
- obj-$(CONFIG_QSEMI_PHY)               += qsemi.o
diff --git a/target/linux/rockchip/patches-5.10/801-char-add-support-for-rockchip-hardware-random-number.patch b/target/linux/rockchip/patches-5.10/801-char-add-support-for-rockchip-hardware-random-number.patch
deleted file mode 100644 (file)
index 16ca627..0000000
+++ /dev/null
@@ -1,45 +0,0 @@
-From e5b5361651940ff5c0c1784dfd0130abec7ab535 Mon Sep 17 00:00:00 2001
-From: wevsty <ty@wevs.org>
-Date: Mon, 24 Aug 2020 02:27:11 +0800
-Subject: [PATCH] char: add support for rockchip hardware random number
- generator
-
-This patch provides hardware random number generator support for all rockchip SOC.
-
-rockchip-rng.c from  https://github.com/rockchip-linux/kernel/blob/develop-4.4/drivers/char/hw_random/rockchip-rng.c
-
-Signed-off-by: wevsty <ty@wevs.org>
----
-
---- a/drivers/char/hw_random/Kconfig
-+++ b/drivers/char/hw_random/Kconfig
-@@ -398,6 +398,19 @@ config HW_RANDOM_STM32
-         If unsure, say N.
-+config HW_RANDOM_ROCKCHIP
-+      tristate "Rockchip Random Number Generator support"
-+      depends on ARCH_ROCKCHIP
-+      default HW_RANDOM
-+      help
-+        This driver provides kernel-side support for the Random Number
-+        Generator hardware found on Rockchip cpus.
-+
-+        To compile this driver as a module, choose M here: the
-+        module will be called rockchip-rng.
-+
-+        If unsure, say Y.
-+
- config HW_RANDOM_PIC32
-       tristate "Microchip PIC32 Random Number Generator support"
-       depends on HW_RANDOM && MACH_PIC32
---- a/drivers/char/hw_random/Makefile
-+++ b/drivers/char/hw_random/Makefile
-@@ -36,6 +36,7 @@ obj-$(CONFIG_HW_RANDOM_IPROC_RNG200) +=
- obj-$(CONFIG_HW_RANDOM_ST) += st-rng.o
- obj-$(CONFIG_HW_RANDOM_XGENE) += xgene-rng.o
- obj-$(CONFIG_HW_RANDOM_STM32) += stm32-rng.o
-+obj-$(CONFIG_HW_RANDOM_ROCKCHIP) += rockchip-rng.o
- obj-$(CONFIG_HW_RANDOM_PIC32) += pic32-rng.o
- obj-$(CONFIG_HW_RANDOM_MESON) += meson-rng.o
- obj-$(CONFIG_HW_RANDOM_CAVIUM) += cavium-rng.o cavium-rng-vf.o
diff --git a/target/linux/rockchip/patches-5.10/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch b/target/linux/rockchip/patches-5.10/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch
deleted file mode 100644 (file)
index 4f18b5c..0000000
+++ /dev/null
@@ -1,50 +0,0 @@
-From e5b5361651940ff5c0c1784dfd0130abec7ab535 Mon Sep 17 00:00:00 2001
-From: wevsty <ty@wevs.org>
-Date: Mon, 24 Aug 2020 02:27:11 +0800
-Subject: [PATCH] arm64: dts: rockchip: add hardware random number generator
- for RK3328 and RK3399
-
-Adding Hardware Random Number Generator Resources to the RK3328 and RK3399.
-
-Signed-off-by: wevsty <ty@wevs.org>
----
-
---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
-@@ -297,6 +297,17 @@
-               status = "disabled";
-       };
-+      rng: rng@ff060000 {
-+              compatible = "rockchip,cryptov1-rng";
-+              reg = <0x0 0xff060000 0x0 0x4000>;
-+
-+              clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO_SLV>;
-+              clock-names = "clk_crypto", "hclk_crypto";
-+              assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO_SLV>;
-+              assigned-clock-rates = <150000000>, <100000000>;
-+              status = "disabled";
-+      };
-+
-       grf: syscon@ff100000 {
-               compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
-               reg = <0x0 0xff100000 0x0 0x1000>;
---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-@@ -1905,6 +1905,16 @@
-               };
-       };
-+      rng: rng@ff8b8000 {
-+              compatible = "rockchip,cryptov1-rng";
-+              reg = <0x0 0xff8b8000 0x0 0x1000>;
-+              clocks = <&cru SCLK_CRYPTO1>, <&cru HCLK_S_CRYPTO1>;
-+              clock-names = "clk_crypto", "hclk_crypto";
-+              assigned-clocks = <&cru SCLK_CRYPTO1>, <&cru HCLK_S_CRYPTO1>;
-+              assigned-clock-rates = <150000000>, <100000000>;
-+              status = "okay";
-+      };
-+
-       gpu: gpu@ff9a0000 {
-               compatible = "rockchip,rk3399-mali", "arm,mali-t860";
-               reg = <0x0 0xff9a0000 0x0 0x10000>;
diff --git a/target/linux/rockchip/patches-5.10/803-PM-devfreq-rockchip-add-devfreq-driver-for-rk3328-dmc.patch b/target/linux/rockchip/patches-5.10/803-PM-devfreq-rockchip-add-devfreq-driver-for-rk3328-dmc.patch
deleted file mode 100644 (file)
index a4b8340..0000000
+++ /dev/null
@@ -1,44 +0,0 @@
-From fcd9629c05f373771e85920e1c1d0ab252617878 Mon Sep 17 00:00:00 2001
-From: hmz007 <hmz007@gmail.com>
-Date: Tue, 19 Nov 2019 13:53:25 +0800
-Subject: [PATCH] PM / devfreq: rockchip: add devfreq driver for rk3328 dmc
-
-Signed-off-by: hmz007 <hmz007@gmail.com>
----
- drivers/devfreq/Kconfig      |  18 +-
- drivers/devfreq/Makefile     |   1 +
- drivers/devfreq/rk3328_dmc.c | 846 +++++++++++++++++++++++++++++++++++
- 3 files changed, 862 insertions(+), 3 deletions(-)
- create mode 100644 drivers/devfreq/rk3328_dmc.c
-
---- a/drivers/devfreq/Kconfig
-+++ b/drivers/devfreq/Kconfig
-@@ -131,6 +131,18 @@ config ARM_TEGRA20_DEVFREQ
-         It reads Memory Controller counters and adjusts the operating
-         frequencies and voltages with OPP support.
-+config ARM_RK3328_DMC_DEVFREQ
-+      tristate "ARM RK3328 DMC DEVFREQ Driver"
-+      depends on ARCH_ROCKCHIP
-+      select DEVFREQ_EVENT_ROCKCHIP_DFI
-+      select DEVFREQ_GOV_SIMPLE_ONDEMAND
-+      select PM_DEVFREQ_EVENT
-+      select PM_OPP
-+      help
-+        This adds the DEVFREQ driver for the RK3328 DMC(Dynamic Memory Controller).
-+        It sets the frequency for the memory controller and reads the usage counts
-+        from hardware.
-+
- config ARM_RK3399_DMC_DEVFREQ
-       tristate "ARM RK3399 DMC DEVFREQ Driver"
-       depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
---- a/drivers/devfreq/Makefile
-+++ b/drivers/devfreq/Makefile
-@@ -12,6 +12,7 @@ obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) +=
- obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ)     += imx-bus.o
- obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ)  += imx8m-ddrc.o
- obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ)  += rk3399_dmc.o
-+obj-$(CONFIG_ARM_RK3328_DMC_DEVFREQ)  += rk3328_dmc.o
- obj-$(CONFIG_ARM_TEGRA_DEVFREQ)               += tegra30-devfreq.o
- obj-$(CONFIG_ARM_TEGRA20_DEVFREQ)     += tegra20-devfreq.o
diff --git a/target/linux/rockchip/patches-5.10/804-clk-rockchip-support-setting-ddr-clock-via-SIP-Version-2-.patch b/target/linux/rockchip/patches-5.10/804-clk-rockchip-support-setting-ddr-clock-via-SIP-Version-2-.patch
deleted file mode 100644 (file)
index 4e688f8..0000000
+++ /dev/null
@@ -1,218 +0,0 @@
-From ce6d3614888e6358466f0e84e248177a6bca5258 Mon Sep 17 00:00:00 2001
-From: Tang Yun ping <typ@rock-chips.com>
-Date: Thu, 4 May 2017 20:49:58 +0800
-Subject: [PATCH] clk: rockchip: support setting ddr clock via SIP Version 2
- APIs
-
-commit 764e893ee82321938fc6f4349e9e7caf06a04410 rockchip.
-
-Signed-off-by: Tang Yun ping <typ@rock-chips.com>
-Signed-off-by: hmz007 <hmz007@gmail.com>
----
- drivers/clk/rockchip/clk-ddr.c      | 130 ++++++++++++++++++++++++++++
- drivers/clk/rockchip/clk-rk3328.c   |   7 +-
- drivers/clk/rockchip/clk.h          |   3 +-
- include/soc/rockchip/rockchip_sip.h |  11 +++
- 4 files changed, 147 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/clk/rockchip/clk-ddr.c b/drivers/clk/rockchip/clk-ddr.c
-index 9273bce4d7b6..555aaf4e758d 100644
---- a/drivers/clk/rockchip/clk-ddr.c
-+++ b/drivers/clk/rockchip/clk-ddr.c
-@@ -87,6 +87,133 @@ static const struct clk_ops rockchip_ddrclk_sip_ops = {
-       .get_parent = rockchip_ddrclk_get_parent,
- };
-+/* See v4.4/include/dt-bindings/display/rk_fb.h */
-+#define SCREEN_NULL                   0
-+#define SCREEN_HDMI                   6
-+
-+static inline int rk_drm_get_lcdc_type(void)
-+{
-+      return SCREEN_NULL;
-+}
-+
-+struct share_params {
-+      u32 hz;
-+      u32 lcdc_type;
-+      u32 vop;
-+      u32 vop_dclk_mode;
-+      u32 sr_idle_en;
-+      u32 addr_mcu_el3;
-+      /*
-+       * 1: need to wait flag1
-+       * 0: never wait flag1
-+       */
-+      u32 wait_flag1;
-+      /*
-+       * 1: need to wait flag1
-+       * 0: never wait flag1
-+       */
-+      u32 wait_flag0;
-+      u32 complt_hwirq;
-+       /* if need, add parameter after */
-+};
-+
-+struct rockchip_ddrclk_data {
-+      u32 inited_flag;
-+      void __iomem *share_memory;
-+};
-+
-+static struct rockchip_ddrclk_data ddr_data;
-+
-+static void rockchip_ddrclk_data_init(void)
-+{
-+      struct arm_smccc_res res;
-+
-+      arm_smccc_smc(ROCKCHIP_SIP_SHARE_MEM,
-+                    1, SHARE_PAGE_TYPE_DDR, 0,
-+                    0, 0, 0, 0, &res);
-+
-+      if (!res.a0) {
-+              ddr_data.share_memory = (void __iomem *)ioremap(res.a1, 1<<12);
-+              ddr_data.inited_flag = 1;
-+      }
-+}
-+
-+static int rockchip_ddrclk_sip_set_rate_v2(struct clk_hw *hw,
-+                                         unsigned long drate,
-+                                         unsigned long prate)
-+{
-+      struct share_params *p;
-+      struct arm_smccc_res res;
-+
-+      if (!ddr_data.inited_flag)
-+              rockchip_ddrclk_data_init();
-+
-+      p = (struct share_params *)ddr_data.share_memory;
-+
-+      p->hz = drate;
-+      p->lcdc_type = rk_drm_get_lcdc_type();
-+      p->wait_flag1 = 1;
-+      p->wait_flag0 = 1;
-+
-+      arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
-+                    SHARE_PAGE_TYPE_DDR, 0,
-+                    ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE,
-+                    0, 0, 0, 0, &res);
-+
-+      if ((int)res.a1 == -6) {
-+              pr_err("%s: timeout, drate = %lumhz\n", __func__, drate/1000000);
-+              /* TODO: rockchip_dmcfreq_wait_complete(); */
-+      }
-+
-+      return res.a0;
-+}
-+
-+static unsigned long rockchip_ddrclk_sip_recalc_rate_v2
-+                      (struct clk_hw *hw, unsigned long parent_rate)
-+{
-+      struct arm_smccc_res res;
-+
-+      arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
-+                    SHARE_PAGE_TYPE_DDR, 0,
-+                    ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE,
-+                    0, 0, 0, 0, &res);
-+      if (!res.a0)
-+              return res.a1;
-+      else
-+              return 0;
-+}
-+
-+static long rockchip_ddrclk_sip_round_rate_v2(struct clk_hw *hw,
-+                                            unsigned long rate,
-+                                            unsigned long *prate)
-+{
-+      struct share_params *p;
-+      struct arm_smccc_res res;
-+
-+      if (!ddr_data.inited_flag)
-+              rockchip_ddrclk_data_init();
-+
-+      p = (struct share_params *)ddr_data.share_memory;
-+
-+      p->hz = rate;
-+
-+      arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
-+                    SHARE_PAGE_TYPE_DDR, 0,
-+                    ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE,
-+                    0, 0, 0, 0, &res);
-+      if (!res.a0)
-+              return res.a1;
-+      else
-+              return 0;
-+}
-+
-+static const struct clk_ops rockchip_ddrclk_sip_ops_v2 = {
-+      .recalc_rate = rockchip_ddrclk_sip_recalc_rate_v2,
-+      .set_rate = rockchip_ddrclk_sip_set_rate_v2,
-+      .round_rate = rockchip_ddrclk_sip_round_rate_v2,
-+      .get_parent = rockchip_ddrclk_get_parent,
-+};
-+
- struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
-                                        const char *const *parent_names,
-                                        u8 num_parents, int mux_offset,
-@@ -114,6 +241,9 @@ struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
-       case ROCKCHIP_DDRCLK_SIP:
-               init.ops = &rockchip_ddrclk_sip_ops;
-               break;
-+      case ROCKCHIP_DDRCLK_SIP_V2:
-+              init.ops = &rockchip_ddrclk_sip_ops_v2;
-+              break;
-       default:
-               pr_err("%s: unsupported ddrclk type %d\n", __func__, ddr_flag);
-               kfree(ddrclk);
-diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c
-index c186a1985bf4..ac6e6163a232 100644
---- a/drivers/clk/rockchip/clk-rk3328.c
-+++ b/drivers/clk/rockchip/clk-rk3328.c
-@@ -314,9 +314,10 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
-                       RK3328_CLKGATE_CON(14), 1, GFLAGS),
-       /* PD_DDR */
--      COMPOSITE(0, "clk_ddr", mux_ddrphy_p, CLK_IGNORE_UNUSED,
--                      RK3328_CLKSEL_CON(3), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
--                      RK3328_CLKGATE_CON(0), 4, GFLAGS),
-+      COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0,
-+                      RK3328_CLKSEL_CON(3), 8, 2, 0, 3,
-+                      ROCKCHIP_DDRCLK_SIP_V2),
-+
-       GATE(0, "clk_ddrmsch", "clk_ddr", CLK_IGNORE_UNUSED,
-                       RK3328_CLKGATE_CON(18), 6, GFLAGS),
-       GATE(0, "clk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
-diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
-index 2271a84124b0..7405aaf965ec 100644
---- a/drivers/clk/rockchip/clk.h
-+++ b/drivers/clk/rockchip/clk.h
-@@ -362,7 +362,8 @@ struct clk *rockchip_clk_register_mmc(const char *name,
-  * DDRCLK flags, including method of setting the rate
-  * ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate.
-  */
--#define ROCKCHIP_DDRCLK_SIP           BIT(0)
-+#define ROCKCHIP_DDRCLK_SIP           0x01
-+#define ROCKCHIP_DDRCLK_SIP_V2                0x03
- struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
-                                        const char *const *parent_names,
-diff --git a/include/soc/rockchip/rockchip_sip.h b/include/soc/rockchip/rockchip_sip.h
-index c46a9ae2a2ab..fa7e0a2d72cc 100644
---- a/include/soc/rockchip/rockchip_sip.h
-+++ b/include/soc/rockchip/rockchip_sip.h
-@@ -16,5 +16,16 @@
- #define ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ      0x06
- #define ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM    0x07
- #define ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD   0x08
-+#define ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION  0x08
-+
-+#define ROCKCHIP_SIP_SHARE_MEM                        0x82000009
-+
-+/* Share mem page types */
-+typedef enum {
-+    SHARE_PAGE_TYPE_INVALID = 0,
-+    SHARE_PAGE_TYPE_UARTDBG,
-+    SHARE_PAGE_TYPE_DDR,
-+    SHARE_PAGE_TYPE_MAX,
-+} share_page_type_t;
- #endif
diff --git a/target/linux/rockchip/patches-5.10/805-PM-devfreq-rockchip-dfi-add-more-soc-support.patch b/target/linux/rockchip/patches-5.10/805-PM-devfreq-rockchip-dfi-add-more-soc-support.patch
deleted file mode 100644 (file)
index 283e4ab..0000000
+++ /dev/null
@@ -1,662 +0,0 @@
-From 4db93c6dad0c71750b86163df2fdb21c35f00d9a Mon Sep 17 00:00:00 2001
-From: hmz007 <hmz007@gmail.com>
-Date: Tue, 19 Nov 2019 12:49:48 +0800
-Subject: [PATCH] PM / devfreq: rockchip-dfi: add more soc support
-
-Signed-off-by: hmz007 <hmz007@gmail.com>
----
- drivers/devfreq/event/rockchip-dfi.c | 554 ++++++++++++++++++++++++---
- 1 file changed, 505 insertions(+), 49 deletions(-)
-
---- a/drivers/devfreq/event/rockchip-dfi.c
-+++ b/drivers/devfreq/event/rockchip-dfi.c
-@@ -18,25 +18,66 @@
- #include <linux/list.h>
- #include <linux/of.h>
--#include <soc/rockchip/rk3399_grf.h>
--
--#define RK3399_DMC_NUM_CH     2
-+#define PX30_PMUGRF_OS_REG2           0x208
-+#define RK3128_GRF_SOC_CON0           0x140
-+#define RK3128_GRF_OS_REG1            0x1cc
-+#define RK3128_GRF_DFI_WRNUM          0x220
-+#define RK3128_GRF_DFI_RDNUM          0x224
-+#define RK3128_GRF_DFI_TIMERVAL               0x22c
-+#define RK3128_DDR_MONITOR_EN         ((1 << (16 + 6)) + (1 << 6))
-+#define RK3128_DDR_MONITOR_DISB               ((1 << (16 + 6)) + (0 << 6))
-+
-+#define RK3288_PMU_SYS_REG2           0x9c
-+#define RK3288_GRF_SOC_CON4           0x254
-+#define RK3288_GRF_SOC_STATUS(n)      (0x280 + (n) * 4)
-+#define RK3288_DFI_EN                 (0x30003 << 14)
-+#define RK3288_DFI_DIS                        (0x30000 << 14)
-+#define RK3288_LPDDR_SEL              (0x10001 << 13)
-+#define RK3288_DDR3_SEL                       (0x10000 << 13)
-+
-+#define RK3328_GRF_OS_REG2            0x5d0
-+
-+#define RK3368_GRF_DDRC0_CON0         0x600
-+#define RK3368_GRF_SOC_STATUS5                0x494
-+#define RK3368_GRF_SOC_STATUS6                0x498
-+#define RK3368_GRF_SOC_STATUS8                0x4a0
-+#define RK3368_GRF_SOC_STATUS9                0x4a4
-+#define RK3368_GRF_SOC_STATUS10               0x4a8
-+#define RK3368_DFI_EN                 (0x30003 << 5)
-+#define RK3368_DFI_DIS                        (0x30000 << 5)
-+
-+#define MAX_DMC_NUM_CH                        2
-+#define READ_DRAMTYPE_INFO(n)         (((n) >> 13) & 0x7)
-+#define READ_CH_INFO(n)                       (((n) >> 28) & 0x3)
- /* DDRMON_CTRL */
--#define DDRMON_CTRL   0x04
--#define CLR_DDRMON_CTRL       (0x1f0000 << 0)
--#define LPDDR4_EN     (0x10001 << 4)
--#define HARDWARE_EN   (0x10001 << 3)
--#define LPDDR3_EN     (0x10001 << 2)
--#define SOFTWARE_EN   (0x10001 << 1)
--#define SOFTWARE_DIS  (0x10000 << 1)
--#define TIME_CNT_EN   (0x10001 << 0)
-+#define DDRMON_CTRL                   0x04
-+#define CLR_DDRMON_CTRL                       (0x3f0000 << 0)
-+#define DDR4_EN                               (0x10001 << 5)
-+#define LPDDR4_EN                     (0x10001 << 4)
-+#define HARDWARE_EN                   (0x10001 << 3)
-+#define LPDDR2_3_EN                   (0x10001 << 2)
-+#define SOFTWARE_EN                   (0x10001 << 1)
-+#define SOFTWARE_DIS                  (0x10000 << 1)
-+#define TIME_CNT_EN                   (0x10001 << 0)
- #define DDRMON_CH0_COUNT_NUM          0x28
- #define DDRMON_CH0_DFI_ACCESS_NUM     0x2c
- #define DDRMON_CH1_COUNT_NUM          0x3c
- #define DDRMON_CH1_DFI_ACCESS_NUM     0x40
-+/* pmu grf */
-+#define PMUGRF_OS_REG2                        0x308
-+
-+enum {
-+      DDR4 = 0,
-+      DDR3 = 3,
-+      LPDDR2 = 5,
-+      LPDDR3 = 6,
-+      LPDDR4 = 7,
-+      UNUSED = 0xFF
-+};
-+
- struct dmc_usage {
-       u32 access;
-       u32 total;
-@@ -50,33 +91,261 @@ struct dmc_usage {
- struct rockchip_dfi {
-       struct devfreq_event_dev *edev;
-       struct devfreq_event_desc *desc;
--      struct dmc_usage ch_usage[RK3399_DMC_NUM_CH];
-+      struct dmc_usage ch_usage[MAX_DMC_NUM_CH];
-       struct device *dev;
-       void __iomem *regs;
-       struct regmap *regmap_pmu;
-+      struct regmap *regmap_grf;
-+      struct regmap *regmap_pmugrf;
-       struct clk *clk;
-+      u32 dram_type;
-+      /*
-+       * available mask, 1: available, 0: not available
-+       * each bit represent a channel
-+       */
-+      u32 ch_msk;
-+};
-+
-+static void rk3128_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
-+{
-+      struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
-+
-+      regmap_write(info->regmap_grf,
-+                   RK3128_GRF_SOC_CON0,
-+                   RK3128_DDR_MONITOR_EN);
-+}
-+
-+static void rk3128_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
-+{
-+      struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
-+
-+      regmap_write(info->regmap_grf,
-+                   RK3128_GRF_SOC_CON0,
-+                   RK3128_DDR_MONITOR_DISB);
-+}
-+
-+static int rk3128_dfi_disable(struct devfreq_event_dev *edev)
-+{
-+      rk3128_dfi_stop_hardware_counter(edev);
-+
-+      return 0;
-+}
-+
-+static int rk3128_dfi_enable(struct devfreq_event_dev *edev)
-+{
-+      rk3128_dfi_start_hardware_counter(edev);
-+
-+      return 0;
-+}
-+
-+static int rk3128_dfi_set_event(struct devfreq_event_dev *edev)
-+{
-+      return 0;
-+}
-+
-+static int rk3128_dfi_get_event(struct devfreq_event_dev *edev,
-+                              struct devfreq_event_data *edata)
-+{
-+      struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
-+      unsigned long flags;
-+      u32 dfi_wr, dfi_rd, dfi_timer;
-+
-+      local_irq_save(flags);
-+
-+      rk3128_dfi_stop_hardware_counter(edev);
-+
-+      regmap_read(info->regmap_grf, RK3128_GRF_DFI_WRNUM, &dfi_wr);
-+      regmap_read(info->regmap_grf, RK3128_GRF_DFI_RDNUM, &dfi_rd);
-+      regmap_read(info->regmap_grf, RK3128_GRF_DFI_TIMERVAL, &dfi_timer);
-+
-+      edata->load_count = (dfi_wr + dfi_rd) * 4;
-+      edata->total_count = dfi_timer;
-+
-+      rk3128_dfi_start_hardware_counter(edev);
-+
-+      local_irq_restore(flags);
-+
-+      return 0;
-+}
-+
-+static const struct devfreq_event_ops rk3128_dfi_ops = {
-+      .disable = rk3128_dfi_disable,
-+      .enable = rk3128_dfi_enable,
-+      .get_event = rk3128_dfi_get_event,
-+      .set_event = rk3128_dfi_set_event,
-+};
-+
-+static void rk3288_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
-+{
-+      struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
-+
-+      regmap_write(info->regmap_grf, RK3288_GRF_SOC_CON4, RK3288_DFI_EN);
-+}
-+
-+static void rk3288_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
-+{
-+      struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
-+
-+      regmap_write(info->regmap_grf, RK3288_GRF_SOC_CON4, RK3288_DFI_DIS);
-+}
-+
-+static int rk3288_dfi_disable(struct devfreq_event_dev *edev)
-+{
-+      rk3288_dfi_stop_hardware_counter(edev);
-+
-+      return 0;
-+}
-+
-+static int rk3288_dfi_enable(struct devfreq_event_dev *edev)
-+{
-+      rk3288_dfi_start_hardware_counter(edev);
-+
-+      return 0;
-+}
-+
-+static int rk3288_dfi_set_event(struct devfreq_event_dev *edev)
-+{
-+      return 0;
-+}
-+
-+static int rk3288_dfi_get_busier_ch(struct devfreq_event_dev *edev)
-+{
-+      struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
-+      u32 tmp, max = 0;
-+      u32 i, busier_ch = 0;
-+      u32 rd_count, wr_count, total_count;
-+
-+      rk3288_dfi_stop_hardware_counter(edev);
-+
-+      /* Find out which channel is busier */
-+      for (i = 0; i < MAX_DMC_NUM_CH; i++) {
-+              if (!(info->ch_msk & BIT(i)))
-+                      continue;
-+              regmap_read(info->regmap_grf,
-+                          RK3288_GRF_SOC_STATUS(11 + i * 4), &wr_count);
-+              regmap_read(info->regmap_grf,
-+                          RK3288_GRF_SOC_STATUS(12 + i * 4), &rd_count);
-+              regmap_read(info->regmap_grf,
-+                          RK3288_GRF_SOC_STATUS(14 + i * 4), &total_count);
-+              info->ch_usage[i].access = (wr_count + rd_count) * 4;
-+              info->ch_usage[i].total = total_count;
-+              tmp = info->ch_usage[i].access;
-+              if (tmp > max) {
-+                      busier_ch = i;
-+                      max = tmp;
-+              }
-+      }
-+      rk3288_dfi_start_hardware_counter(edev);
-+
-+      return busier_ch;
-+}
-+
-+static int rk3288_dfi_get_event(struct devfreq_event_dev *edev,
-+                              struct devfreq_event_data *edata)
-+{
-+      struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
-+      int busier_ch;
-+      unsigned long flags;
-+
-+      local_irq_save(flags);
-+      busier_ch = rk3288_dfi_get_busier_ch(edev);
-+      local_irq_restore(flags);
-+
-+      edata->load_count = info->ch_usage[busier_ch].access;
-+      edata->total_count = info->ch_usage[busier_ch].total;
-+
-+      return 0;
-+}
-+
-+static const struct devfreq_event_ops rk3288_dfi_ops = {
-+      .disable = rk3288_dfi_disable,
-+      .enable = rk3288_dfi_enable,
-+      .get_event = rk3288_dfi_get_event,
-+      .set_event = rk3288_dfi_set_event,
-+};
-+
-+static void rk3368_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
-+{
-+      struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
-+
-+      regmap_write(info->regmap_grf, RK3368_GRF_DDRC0_CON0, RK3368_DFI_EN);
-+}
-+
-+static void rk3368_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
-+{
-+      struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
-+
-+      regmap_write(info->regmap_grf, RK3368_GRF_DDRC0_CON0, RK3368_DFI_DIS);
-+}
-+
-+static int rk3368_dfi_disable(struct devfreq_event_dev *edev)
-+{
-+      rk3368_dfi_stop_hardware_counter(edev);
-+
-+      return 0;
-+}
-+
-+static int rk3368_dfi_enable(struct devfreq_event_dev *edev)
-+{
-+      rk3368_dfi_start_hardware_counter(edev);
-+
-+      return 0;
-+}
-+
-+static int rk3368_dfi_set_event(struct devfreq_event_dev *edev)
-+{
-+      return 0;
-+}
-+
-+static int rk3368_dfi_get_event(struct devfreq_event_dev *edev,
-+                              struct devfreq_event_data *edata)
-+{
-+      struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
-+      unsigned long flags;
-+      u32 dfi0_wr, dfi0_rd, dfi1_wr, dfi1_rd, dfi_timer;
-+
-+      local_irq_save(flags);
-+
-+      rk3368_dfi_stop_hardware_counter(edev);
-+
-+      regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS5, &dfi0_wr);
-+      regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS6, &dfi0_rd);
-+      regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS9, &dfi1_wr);
-+      regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS10, &dfi1_rd);
-+      regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS8, &dfi_timer);
-+
-+      edata->load_count = (dfi0_wr + dfi0_rd + dfi1_wr + dfi1_rd) * 2;
-+      edata->total_count = dfi_timer;
-+
-+      rk3368_dfi_start_hardware_counter(edev);
-+
-+      local_irq_restore(flags);
-+
-+      return 0;
-+}
-+
-+static const struct devfreq_event_ops rk3368_dfi_ops = {
-+      .disable = rk3368_dfi_disable,
-+      .enable = rk3368_dfi_enable,
-+      .get_event = rk3368_dfi_get_event,
-+      .set_event = rk3368_dfi_set_event,
- };
- static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
- {
-       struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
-       void __iomem *dfi_regs = info->regs;
--      u32 val;
--      u32 ddr_type;
--
--      /* get ddr type */
--      regmap_read(info->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
--      ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
--                  RK3399_PMUGRF_DDRTYPE_MASK;
-       /* clear DDRMON_CTRL setting */
-       writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);
-       /* set ddr type to dfi */
--      if (ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR3)
--              writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);
--      else if (ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR4)
-+      if (info->dram_type == LPDDR3 || info->dram_type == LPDDR2)
-+              writel_relaxed(LPDDR2_3_EN, dfi_regs + DDRMON_CTRL);
-+      else if (info->dram_type == LPDDR4)
-               writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
-+      else if (info->dram_type == DDR4)
-+              writel_relaxed(DDR4_EN, dfi_regs + DDRMON_CTRL);
-       /* enable count, use software mode */
-       writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL);
-@@ -100,12 +369,22 @@ static int rockchip_dfi_get_busier_ch(st
-       rockchip_dfi_stop_hardware_counter(edev);
-       /* Find out which channel is busier */
--      for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
--              info->ch_usage[i].access = readl_relaxed(dfi_regs +
--                              DDRMON_CH0_DFI_ACCESS_NUM + i * 20) * 4;
-+      for (i = 0; i < MAX_DMC_NUM_CH; i++) {
-+              if (!(info->ch_msk & BIT(i)))
-+                      continue;
-+
-               info->ch_usage[i].total = readl_relaxed(dfi_regs +
-                               DDRMON_CH0_COUNT_NUM + i * 20);
--              tmp = info->ch_usage[i].access;
-+
-+              /* LPDDR4 BL = 16,other DDR type BL = 8 */
-+              tmp = readl_relaxed(dfi_regs +
-+                              DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
-+              if (info->dram_type == LPDDR4)
-+                      tmp *= 8;
-+              else
-+                      tmp *= 4;
-+              info->ch_usage[i].access = tmp;
-+
-               if (tmp > max) {
-                       busier_ch = i;
-                       max = tmp;
-@@ -121,7 +400,8 @@ static int rockchip_dfi_disable(struct d
-       struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
-       rockchip_dfi_stop_hardware_counter(edev);
--      clk_disable_unprepare(info->clk);
-+      if (info->clk)
-+              clk_disable_unprepare(info->clk);
-       return 0;
- }
-@@ -131,10 +411,13 @@ static int rockchip_dfi_enable(struct de
-       struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
-       int ret;
--      ret = clk_prepare_enable(info->clk);
--      if (ret) {
--              dev_err(&edev->dev, "failed to enable dfi clk: %d\n", ret);
--              return ret;
-+      if (info->clk) {
-+              ret = clk_prepare_enable(info->clk);
-+              if (ret) {
-+                      dev_err(&edev->dev, "failed to enable dfi clk: %d\n",
-+                              ret);
-+                      return ret;
-+              }
-       }
-       rockchip_dfi_start_hardware_counter(edev);
-@@ -151,8 +434,11 @@ static int rockchip_dfi_get_event(struct
- {
-       struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
-       int busier_ch;
-+      unsigned long flags;
-+      local_irq_save(flags);
-       busier_ch = rockchip_dfi_get_busier_ch(edev);
-+      local_irq_restore(flags);
-       edata->load_count = info->ch_usage[busier_ch].access;
-       edata->total_count = info->ch_usage[busier_ch].total;
-@@ -167,22 +453,116 @@ static const struct devfreq_event_ops ro
-       .set_event = rockchip_dfi_set_event,
- };
--static const struct of_device_id rockchip_dfi_id_match[] = {
--      { .compatible = "rockchip,rk3399-dfi" },
--      { },
--};
--MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match);
-+static __init int px30_dfi_init(struct platform_device *pdev,
-+                                struct rockchip_dfi *data,
-+                                struct devfreq_event_desc *desc)
-+{
-+      struct device_node *np = pdev->dev.of_node, *node;
-+      struct resource *res;
-+      u32 val;
--static int rockchip_dfi_probe(struct platform_device *pdev)
-+      res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+      data->regs = devm_ioremap_resource(&pdev->dev, res);
-+      if (IS_ERR(data->regs))
-+              return PTR_ERR(data->regs);
-+
-+      node = of_parse_phandle(np, "rockchip,pmugrf", 0);
-+      if (node) {
-+              data->regmap_pmugrf = syscon_node_to_regmap(node);
-+              if (IS_ERR(data->regmap_pmugrf))
-+                      return PTR_ERR(data->regmap_pmugrf);
-+      }
-+
-+      regmap_read(data->regmap_pmugrf, PX30_PMUGRF_OS_REG2, &val);
-+      data->dram_type = READ_DRAMTYPE_INFO(val);
-+      data->ch_msk = 1;
-+      data->clk = NULL;
-+
-+      desc->ops = &rockchip_dfi_ops;
-+
-+      return 0;
-+}
-+
-+static __init int rk3128_dfi_init(struct platform_device *pdev,
-+                                struct rockchip_dfi *data,
-+                                struct devfreq_event_desc *desc)
- {
--      struct device *dev = &pdev->dev;
--      struct rockchip_dfi *data;
--      struct devfreq_event_desc *desc;
-       struct device_node *np = pdev->dev.of_node, *node;
--      data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL);
--      if (!data)
--              return -ENOMEM;
-+      node = of_parse_phandle(np, "rockchip,grf", 0);
-+      if (node) {
-+              data->regmap_grf = syscon_node_to_regmap(node);
-+              if (IS_ERR(data->regmap_grf))
-+                      return PTR_ERR(data->regmap_grf);
-+      }
-+
-+      desc->ops = &rk3128_dfi_ops;
-+
-+      return 0;
-+}
-+
-+static __init int rk3288_dfi_init(struct platform_device *pdev,
-+                                struct rockchip_dfi *data,
-+                                struct devfreq_event_desc *desc)
-+{
-+      struct device_node *np = pdev->dev.of_node, *node;
-+      u32 val;
-+
-+      node = of_parse_phandle(np, "rockchip,pmu", 0);
-+      if (node) {
-+              data->regmap_pmu = syscon_node_to_regmap(node);
-+              if (IS_ERR(data->regmap_pmu))
-+                      return PTR_ERR(data->regmap_pmu);
-+      }
-+
-+      node = of_parse_phandle(np, "rockchip,grf", 0);
-+      if (node) {
-+              data->regmap_grf = syscon_node_to_regmap(node);
-+              if (IS_ERR(data->regmap_grf))
-+                      return PTR_ERR(data->regmap_grf);
-+      }
-+
-+      regmap_read(data->regmap_pmu, RK3288_PMU_SYS_REG2, &val);
-+      data->dram_type = READ_DRAMTYPE_INFO(val);
-+      data->ch_msk = READ_CH_INFO(val);
-+
-+      if (data->dram_type == DDR3)
-+              regmap_write(data->regmap_grf, RK3288_GRF_SOC_CON4,
-+                           RK3288_DDR3_SEL);
-+      else
-+              regmap_write(data->regmap_grf, RK3288_GRF_SOC_CON4,
-+                           RK3288_LPDDR_SEL);
-+
-+      desc->ops = &rk3288_dfi_ops;
-+
-+      return 0;
-+}
-+
-+static __init int rk3368_dfi_init(struct platform_device *pdev,
-+                                struct rockchip_dfi *data,
-+                                struct devfreq_event_desc *desc)
-+{
-+      struct device *dev = &pdev->dev;
-+
-+      if (!dev->parent || !dev->parent->of_node)
-+              return -EINVAL;
-+
-+      data->regmap_grf = syscon_node_to_regmap(dev->parent->of_node);
-+      if (IS_ERR(data->regmap_grf))
-+              return PTR_ERR(data->regmap_grf);
-+
-+      desc->ops = &rk3368_dfi_ops;
-+
-+      return 0;
-+}
-+
-+static __init int rockchip_dfi_init(struct platform_device *pdev,
-+                                  struct rockchip_dfi *data,
-+                                  struct devfreq_event_desc *desc)
-+{
-+      struct device *dev = &pdev->dev;
-+      struct device_node *np = pdev->dev.of_node, *node;
-+      u32 val;
-       data->regs = devm_platform_ioremap_resource(pdev, 0);
-       if (IS_ERR(data->regs))
-@@ -202,21 +582,97 @@ static int rockchip_dfi_probe(struct pla
-               if (IS_ERR(data->regmap_pmu))
-                       return PTR_ERR(data->regmap_pmu);
-       }
--      data->dev = dev;
-+
-+      regmap_read(data->regmap_pmu, PMUGRF_OS_REG2, &val);
-+      data->dram_type = READ_DRAMTYPE_INFO(val);
-+      data->ch_msk = READ_CH_INFO(val);
-+
-+      desc->ops = &rockchip_dfi_ops;
-+
-+      return 0;
-+}
-+
-+static __init int rk3328_dfi_init(struct platform_device *pdev,
-+                                struct rockchip_dfi *data,
-+                                struct devfreq_event_desc *desc)
-+{
-+      struct device_node *np = pdev->dev.of_node, *node;
-+      struct resource *res;
-+      u32 val;
-+
-+      res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+      data->regs = devm_ioremap_resource(&pdev->dev, res);
-+      if (IS_ERR(data->regs))
-+              return PTR_ERR(data->regs);
-+
-+      node = of_parse_phandle(np, "rockchip,grf", 0);
-+      if (node) {
-+              data->regmap_grf = syscon_node_to_regmap(node);
-+              if (IS_ERR(data->regmap_grf))
-+                      return PTR_ERR(data->regmap_grf);
-+      }
-+
-+      regmap_read(data->regmap_grf, RK3328_GRF_OS_REG2, &val);
-+      data->dram_type = READ_DRAMTYPE_INFO(val);
-+      data->ch_msk = 1;
-+      data->clk = NULL;
-+
-+      desc->ops = &rockchip_dfi_ops;
-+
-+      return 0;
-+}
-+
-+static const struct of_device_id rockchip_dfi_id_match[] = {
-+      { .compatible = "rockchip,px30-dfi", .data = px30_dfi_init },
-+      { .compatible = "rockchip,rk1808-dfi", .data = px30_dfi_init },
-+      { .compatible = "rockchip,rk3128-dfi", .data = rk3128_dfi_init },
-+      { .compatible = "rockchip,rk3288-dfi", .data = rk3288_dfi_init },
-+      { .compatible = "rockchip,rk3328-dfi", .data = rk3328_dfi_init },
-+      { .compatible = "rockchip,rk3368-dfi", .data = rk3368_dfi_init },
-+      { .compatible = "rockchip,rk3399-dfi", .data = rockchip_dfi_init },
-+      { },
-+};
-+MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match);
-+
-+static int rockchip_dfi_probe(struct platform_device *pdev)
-+{
-+      struct device *dev = &pdev->dev;
-+      struct rockchip_dfi *data;
-+      struct devfreq_event_desc *desc;
-+      struct device_node *np = pdev->dev.of_node;
-+      const struct of_device_id *match;
-+      int (*init)(struct platform_device *pdev, struct rockchip_dfi *data,
-+                  struct devfreq_event_desc *desc);
-+
-+      data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL);
-+      if (!data)
-+              return -ENOMEM;
-       desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
-       if (!desc)
-               return -ENOMEM;
--      desc->ops = &rockchip_dfi_ops;
-+      match = of_match_node(rockchip_dfi_id_match, pdev->dev.of_node);
-+      if (match) {
-+              init = match->data;
-+              if (init) {
-+                      if (init(pdev, data, desc))
-+                              return -EINVAL;
-+              } else {
-+                      return 0;
-+              }
-+      } else {
-+              return 0;
-+      }
-+
-       desc->driver_data = data;
-       desc->name = np->name;
-       data->desc = desc;
-+      data->dev = dev;
--      data->edev = devm_devfreq_event_add_edev(&pdev->dev, desc);
-+      data->edev = devm_devfreq_event_add_edev(dev, desc);
-       if (IS_ERR(data->edev)) {
--              dev_err(&pdev->dev,
--                      "failed to add devfreq-event device\n");
-+              dev_err(dev, "failed to add devfreq-event device\n");
-               return PTR_ERR(data->edev);
-       }
diff --git a/target/linux/rockchip/patches-5.10/806-arm64-dts-rockchip-rk3328-add-dfi-node.patch b/target/linux/rockchip/patches-5.10/806-arm64-dts-rockchip-rk3328-add-dfi-node.patch
deleted file mode 100644 (file)
index 8a5222d..0000000
+++ /dev/null
@@ -1,27 +0,0 @@
-From f9ae6e992d3d9e80357fee7d65ba0fe2dd37ae1f Mon Sep 17 00:00:00 2001
-From: hmz007 <hmz007@gmail.com>
-Date: Tue, 19 Nov 2019 14:21:51 +0800
-Subject: [PATCH] arm64: dts: rockchip: rk3328: add dfi node
-
-Signed-off-by: hmz007 <hmz007@gmail.com>
-[adjusted commit title]
-Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
----
- arch/arm64/boot/dts/rockchip/rk3328.dtsi   |   7 +++++++
-
---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
-@@ -1022,6 +1022,13 @@
-               };
-       };
-+      dfi: dfi@ff790000 {
-+              reg = <0x00 0xff790000 0x00 0x400>;
-+              compatible = "rockchip,rk3328-dfi";
-+              rockchip,grf = <&grf>;
-+              status = "disabled";
-+      };
-+
-       gic: interrupt-controller@ff811000 {
-               compatible = "arm,gic-400";
-               #interrupt-cells = <3>;
diff --git a/target/linux/rockchip/patches-5.10/807-arm64-dts-nanopi-r2s-add-rk3328-dmc-relate-node.patch b/target/linux/rockchip/patches-5.10/807-arm64-dts-nanopi-r2s-add-rk3328-dmc-relate-node.patch
deleted file mode 100644 (file)
index 4933f0b..0000000
+++ /dev/null
@@ -1,126 +0,0 @@
-From f9ae6e992d3d9e80357fee7d65ba0fe2dd37ae1f Mon Sep 17 00:00:00 2001
-From: hmz007 <hmz007@gmail.com>
-Date: Tue, 19 Nov 2019 14:21:51 +0800
-Subject: [PATCH] arm64: dts: nanopi-r2: add rk3328-dmc relate node
-
-Signed-off-by: hmz007 <hmz007@gmail.com>
----
- .../rockchip/rk3328-dram-default-timing.dtsi  | 311 ++++++++++++++++++
- .../dts/rockchip/rk3328-nanopi-r2-common.dtsi |  85 ++++-
- include/dt-bindings/clock/rockchip-ddr.h      |  63 ++++
- include/dt-bindings/memory/rk3328-dram.h      | 159 +++++++++
- 4 files changed, 617 insertions(+), 1 deletion(-)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-dram-default-timing.dtsi
- create mode 100644 include/dt-bindings/clock/rockchip-ddr.h
- create mode 100644 include/dt-bindings/memory/rk3328-dram.h
-
---- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
-@@ -7,6 +7,7 @@
- #include <dt-bindings/input/input.h>
- #include <dt-bindings/gpio/gpio.h>
-+#include "rk3328-dram-default-timing.dtsi"
- #include "rk3328.dtsi"
- / {
-@@ -115,6 +116,72 @@
-               regulator-min-microvolt = <5000000>;
-               regulator-max-microvolt = <5000000>;
-       };
-+
-+      dmc: dmc {
-+              compatible = "rockchip,rk3328-dmc";
-+              devfreq-events = <&dfi>;
-+              center-supply = <&vdd_log>;
-+              clocks = <&cru SCLK_DDRCLK>;
-+              clock-names = "dmc_clk";
-+              operating-points-v2 = <&dmc_opp_table>;
-+              ddr_timing = <&ddr_timing>;
-+              upthreshold = <40>;
-+              downdifferential = <20>;
-+              auto-min-freq = <786000>;
-+              auto-freq-en = <0>;
-+              #cooling-cells = <2>;
-+              status = "okay";
-+
-+              ddr_power_model: ddr_power_model {
-+                      compatible = "ddr_power_model";
-+                      dynamic-power-coefficient = <120>;
-+                      static-power-coefficient = <200>;
-+                      ts = <32000 4700 (-80) 2>;
-+                      thermal-zone = "soc-thermal";
-+              };
-+      };
-+
-+      dmc_opp_table: dmc-opp-table {
-+              compatible = "operating-points-v2";
-+
-+              rockchip,leakage-voltage-sel = <
-+                      1   10    0
-+                      11  254   1
-+              >;
-+              nvmem-cells = <&logic_leakage>;
-+              nvmem-cell-names = "ddr_leakage";
-+
-+              opp-786000000 {
-+                      opp-hz = /bits/ 64 <786000000>;
-+                      opp-microvolt = <1075000>;
-+                      opp-microvolt-L0 = <1075000>;
-+                      opp-microvolt-L1 = <1050000>;
-+              };
-+              opp-798000000 {
-+                      opp-hz = /bits/ 64 <798000000>;
-+                      opp-microvolt = <1075000>;
-+                      opp-microvolt-L0 = <1075000>;
-+                      opp-microvolt-L1 = <1050000>;
-+              };
-+              opp-840000000 {
-+                      opp-hz = /bits/ 64 <840000000>;
-+                      opp-microvolt = <1075000>;
-+                      opp-microvolt-L0 = <1075000>;
-+                      opp-microvolt-L1 = <1050000>;
-+              };
-+              opp-924000000 {
-+                      opp-hz = /bits/ 64 <924000000>;
-+                      opp-microvolt = <1100000>;
-+                      opp-microvolt-L0 = <1100000>;
-+                      opp-microvolt-L1 = <1075000>;
-+              };
-+              opp-1056000000 {
-+                      opp-hz = /bits/ 64 <1056000000>;
-+                      opp-microvolt = <1175000>;
-+                      opp-microvolt-L0 = <1175000>;
-+                      opp-microvolt-L1 = <1150000>;
-+              };
-+      };
- };
- &cpu0 {
-@@ -137,6 +204,10 @@
-       status = "disabled";
- };
-+&dfi {
-+      status = "okay";
-+};
-+
- &gmac2io {
-       assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
-       assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
-@@ -202,6 +273,7 @@
-                               regulator-name = "vdd_log";
-                               regulator-always-on;
-                               regulator-boot-on;
-+                              regulator-init-microvolt = <1075000>;
-                               regulator-min-microvolt = <712500>;
-                               regulator-max-microvolt = <1450000>;
-                               regulator-ramp-delay = <12500>;
-@@ -216,6 +288,7 @@
-                               regulator-name = "vdd_arm";
-                               regulator-always-on;
-                               regulator-boot-on;
-+                              regulator-init-microvolt = <1225000>;
-                               regulator-min-microvolt = <712500>;
-                               regulator-max-microvolt = <1450000>;
-                               regulator-ramp-delay = <12500>;
diff --git a/target/linux/rockchip/patches-5.10/911-kernel-dma-adjust-default-coherent_pool-to-2MiB.patch b/target/linux/rockchip/patches-5.10/911-kernel-dma-adjust-default-coherent_pool-to-2MiB.patch
deleted file mode 100644 (file)
index f589ce2..0000000
+++ /dev/null
@@ -1,28 +0,0 @@
-From 16bdf3e76fec6ddb44f1fcf221139fb39d225031 Mon Sep 17 00:00:00 2001
-From: Igor Pecovnik <igor.pecovnik@gmail.com>
-Date: Sat, 2 Jan 2021 05:23:55 +0000
-Subject: [PATCH] kernel: dma: adjust default coherent_pool to 2MiB
-
----
- kernel/dma/pool.c | 8 +++-----
- 1 file changed, 3 insertions(+), 5 deletions(-)
-
---- a/kernel/dma/pool.c
-+++ b/kernel/dma/pool.c
-@@ -192,13 +192,11 @@ static int __init dma_atomic_pool_init(v
-       int ret = 0;
-       /*
--       * If coherent_pool was not used on the command line, default the pool
--       * sizes to 128KB per 1GB of memory, min 128KB, max MAX_ORDER-1.
-+       * Always use 2MiB as default pool size.
-+       * See: https://forum.armbian.com/topic/4811-uas-mainline-kernel-coherent-pool-memory-size/
-        */
-       if (!atomic_pool_size) {
--              unsigned long pages = totalram_pages() / (SZ_1G / SZ_128K);
--              pages = min_t(unsigned long, pages, MAX_ORDER_NR_PAGES);
--              atomic_pool_size = max_t(size_t, pages << PAGE_SHIFT, SZ_128K);
-+              atomic_pool_size = SZ_2M;
-       }
-       INIT_WORK(&atomic_pool_work, atomic_pool_work_fn);
diff --git a/target/linux/rockchip/patches-5.10/991-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch b/target/linux/rockchip/patches-5.10/991-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch
deleted file mode 100644 (file)
index c85da5f..0000000
+++ /dev/null
@@ -1,44 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Leonidas P. Papadakos <papadakospan@gmail.com>
-Date: Fri, 1 Mar 2019 21:55:53 +0200
-Subject: [PATCH v2] arm64: dts: rockchip: add more cpu operating points for
- RK3328
-
-This allows for greater max frequency on rk3328 boards,
-increasing performance.
-
-It has been included in Armbian (a linux distibution for ARM boards)
-for a while now without any reported issues
-
-https://github.com/armbian/build/blob/master/patch/kernel/rockchip64-default/enable-1392mhz-opp.patch
-https://github.com/armbian/build/blob/master/patch/kernel/rockchip64-default/enable-1512mhz-opp.patch
-
-Signed-off-by: Leonidas P. Papadakos <papadakospan@gmail.com>
----
- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 15 +++++++++++++++
- 1 files changed, 15 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
-@@ -140,6 +140,21 @@
-                       opp-microvolt = <1300000>;
-                       clock-latency-ns = <40000>;
-               };
-+              opp-1392000000 {
-+                      opp-hz = /bits/ 64 <1392000000>;
-+                      opp-microvolt = <1350000>;
-+                      clock-latency-ns = <40000>;
-+              };
-+              opp-1512000000 {
-+                      opp-hz = /bits/ 64 <1512000000>;
-+                      opp-microvolt = <1400000>;
-+                      clock-latency-ns = <40000>;
-+              };
-+              opp-1608000000 {
-+                      opp-hz = /bits/ 64 <1608000000>;
-+                      opp-microvolt = <1450000>;
-+                      clock-latency-ns = <40000>;
-+              };
-       };
-       amba: bus {
diff --git a/target/linux/rockchip/patches-5.10/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz.patch b/target/linux/rockchip/patches-5.10/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz.patch
deleted file mode 100644 (file)
index 12cb932..0000000
+++ /dev/null
@@ -1,46 +0,0 @@
-From 04202df5cb497b1934c95211cf43784ef62245a4 Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@immortalwrt.org>
-Date: Mon, 18 Oct 2021 12:47:30 +0800
-Subject: [PATCH] rockchip: rk3399: overclock to 2.2/1.8 GHz
-
-It's stable enough to overclock cpu frequency to 2.2/1.8 GHz,
-and for better performance.
-
-Co-development-by: gzelvis <gzelvis@gmail.com>
-Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
----
- arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi | 16 ++++++++++++++++
- 1 file changed, 16 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
-@@ -33,6 +33,14 @@
-                       opp-hz = /bits/ 64 <1416000000>;
-                       opp-microvolt = <1125000>;
-               };
-+              opp06 {
-+                      opp-hz = /bits/ 64 <1608000000>;
-+                      opp-microvolt = <1225000>;
-+              };
-+              opp07 {
-+                      opp-hz = /bits/ 64 <1800000000>;
-+                      opp-microvolt = <1275000>;
-+              };
-       };
-       cluster1_opp: opp-table1 {
-@@ -72,6 +80,14 @@
-                       opp-hz = /bits/ 64 <1800000000>;
-                       opp-microvolt = <1200000>;
-               };
-+              opp08 {
-+                      opp-hz = /bits/ 64 <2016000000>;
-+                      opp-microvolt = <1250000>;
-+              };
-+              opp09 {
-+                      opp-hz = /bits/ 64 <2208000000>;
-+                      opp-microvolt = <1325000>;
-+              };
-       };
-       gpu_opp_table: opp-table2 {