apu address set bug fixex!!!

[motonesfpga/motonesfpga.git] / de1_nes / simulation / modelsim / de1_nes_run_msim_gate_vhdl.do

diff --git a/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do b/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do
index a518878..d6ee878 100644 (file)
--- a/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do
+++ b/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do
@@ -40,59 +40,64 @@ add wave -label ea_carry   -radix decimal -unsigned  sim:/testbench_motones_sim/
 \r
 \r
 \r
-add wave -divider regs\r
-\r
+#add wave -divider regs\r
+#\r
 #add wave -label pcl  -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_ctrl\r
 #add wave -label pch  -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_mask\r
-\r
-add wave -label acc    -radix hex sim:/testbench_motones_sim/sim_board/dbg_acc\r
-add wave -label sp     -radix hex sim:/testbench_motones_sim/sim_board/dbg_sp\r
-add wave -label x      -radix hex sim:/testbench_motones_sim/sim_board/dbg_x\r
-add wave -label y      -radix hex sim:/testbench_motones_sim/sim_board/dbg_y\r
-add wave -label status -radix hex sim:/testbench_motones_sim/sim_board/dbg_status\r
-\r
-\r
-#add wave -divider ppu\r
-#add wave -label ppu_clk    sim:/testbench_motones_sim/sim_board/dbg_ppu_clk\r
-#add wave -label ppu_ce_n          sim:/testbench_motones_sim/sim_board/dbg_ppu_ce_n\r
-#add wave -label ppu_ctrl  -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_ctrl\r
-#add wave -label ppu_mask  -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_mask\r
-##add wave -label ppu_status   -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_status\r
-#add wave -label ppu_addr -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_addr\r
-#add wave -label ppu_data -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_data\r
-\r
-\r
-###add wave -divider vga_pos\r
-####add wave -label nes_x           -radix decimal -unsigned  sim:/testbench_motones_sim/sim_board/dbg_ppu_addr\r
-###add wave -label dbg_disp_nt     -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_nt\r
-###add wave -label dbg_disp_attr   -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_attr\r
-####add wave -label dbg_disp_ptn_h  -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_h\r
-####add wave -label dbg_disp_ptn_l  -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_l\r
-###\r
-###add wave -divider vram\r
-###add wave -label ale sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(0)\r
-###add wave -label rd_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(1)\r
-###add wave -label wr_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(2)\r
-###add wave -label nt0_ce_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(3)\r
-###\r
-###add wave  -radix hex -label v_addr sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_l\r
-###add wave  -radix hex -label vram_ad sim:/testbench_motones_sim/sim_board/dbg_vram_ad\r
-###\r
-###\r
-###add wave -label plt_ce_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(5)\r
-###add wave -label plt_r_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(4)\r
-###add wave -label plt_w_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(3)\r
-###add wave  -radix hex -label plt_addr {sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_h(12 downto 8)}\r
-###add wave  -radix hex -label plt_data {sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_h(7 downto 0)}\r
-###\r
-###\r
-###\r
-###add wave -divider vga_out\r
-###add wave -label h_sync_n    sim:/testbench_motones_sim/sim_board/v_sync_n\r
-###add wave -label v_sync_n    sim:/testbench_motones_sim/sim_board/h_sync_n\r
-###add wave -label r           -radix hex sim:/testbench_motones_sim/sim_board/r\r
-###add wave -label g           -radix hex sim:/testbench_motones_sim/sim_board/g\r
-###add wave -label b           -radix hex sim:/testbench_motones_sim/sim_board/b\r
+#\r
+#add wave -label acc    -radix hex sim:/testbench_motones_sim/sim_board/dbg_acc\r
+#add wave -label sp     -radix hex sim:/testbench_motones_sim/sim_board/dbg_sp\r
+#add wave -label x      -radix hex sim:/testbench_motones_sim/sim_board/dbg_x\r
+#add wave -label y      -radix hex sim:/testbench_motones_sim/sim_board/dbg_y\r
+#add wave -label status -radix hex sim:/testbench_motones_sim/sim_board/dbg_status\r
+\r
+\r
+add wave -divider ppu\r
+add wave -label ppu_clk    sim:/testbench_motones_sim/sim_board/dbg_ppu_clk\r
+add wave -label ppu_ce_n          sim:/testbench_motones_sim/sim_board/dbg_ppu_ce_n\r
+add wave -label ppu_ctrl  -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_ctrl\r
+add wave -label ppu_mask  -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_mask\r
+add wave -label ppu_status   -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_status\r
+add wave -label ppu_addr -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_addr\r
+add wave -label ppu_data -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_data\r
+\r
+\r
+#add wave -divider vga_pos\r
+##add wave -label nes_x           -radix decimal -unsigned  sim:/testbench_motones_sim/sim_board/dbg_ppu_addr\r
+#add wave -label dbg_disp_nt     -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_nt\r
+#add wave -label dbg_disp_attr   -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_attr\r
+##add wave -label dbg_disp_ptn_h  -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_h\r
+##add wave -label dbg_disp_ptn_l  -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_l\r
+#\r
+add wave -divider vram\r
+#add wave -label ale sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(0)\r
+#add wave -label rd_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(1)\r
+#add wave -label wr_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(2)\r
+#add wave -label nt0_ce_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(3)\r
+\r
+add wave  -radix hex -label v_addr {sim:/testbench_motones_sim/sim_board/dbg_sp(5 downto 0)}\r
+add wave  -radix hex -label vram_ad sim:/testbench_motones_sim/sim_board/dbg_vram_ad\r
+\r
+#add wave -label plt_ce_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(5)\r
+#add wave -label plt_r_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(4)\r
+#add wave -label plt_w_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(3)\r
+add wave -label oam_ce_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(2)\r
+add wave -label oam_r_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(1)\r
+add wave -label oam_w_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(0)\r
+#add wave  -radix hex -label plt_addr {sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_h(12 downto 8)}\r
+#add wave  -radix hex -label plt_data {sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_h(7 downto 0)}\r
+\r
+\r
+add wave -divider oam\r
+add wave  -radix hex -label p_oam_addr {sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_l (7 downto 0)}\r
+add wave  -radix hex -label p_oam_data {sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_l (15 downto 8)}\r
+\r
+#add wave -divider vga_out\r
+#add wave -label h_sync_n    sim:/testbench_motones_sim/sim_board/v_sync_n\r
+#add wave -label v_sync_n    sim:/testbench_motones_sim/sim_board/h_sync_n\r
+#add wave -label r           -radix hex sim:/testbench_motones_sim/sim_board/r\r
+#add wave -label g           -radix hex sim:/testbench_motones_sim/sim_board/g\r
+#add wave -label b           -radix hex sim:/testbench_motones_sim/sim_board/b\r
 \r
 \r
 view structure\r