gate level simulation ok

[motonesfpga/motonesfpga.git] / de1_nes / simulation / modelsim / motones_modelsim.mpf

diff --git a/de1_nes/simulation/modelsim/motones_modelsim.mpf b/de1_nes/simulation/modelsim/motones_modelsim.mpf
index 6dc37d9..e7e1e49 100644 (file)
--- a/de1_nes/simulation/modelsim/motones_modelsim.mpf
+++ b/de1_nes/simulation/modelsim/motones_modelsim.mpf
@@ -127,7 +127,7 @@ cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive
 hardcopyiv_hssi_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_hssi\r
 hardcopyiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_pcie_hip\r
 \r
-work = rtl_work\r
+work = gate_work\r
 [vcom]\r
 ; VHDL93 variable selects language version as the default. \r
 ; Default is VHDL-2002.\r