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(parent: 92a07ea) | patch
sdc added. must rework for timing again... all clocks must be aligned on the risigg...
authorastoria-d <astoria-d@mail.goo.ne.jp>
Sat, 6 Aug 2016 03:29:26 +0000 (12:29 +0900)
committerastoria-d <astoria-d@mail.goo.ne.jp>
Sat, 6 Aug 2016 03:29:26 +0000 (12:29 +0900)
commit5a66edc0a926ba688db508f25645e0ca458a9802
tree5c06c259f4d4d03c79636bae77dee8d27785abb7tree | snapshot
parent92a07ead4852f095d15f3b3a03ea564a928b249dcommit | diff
sdc added. must rework for timing again... all clocks must be aligned on the risigg edge.
de1_nes/de1_nes.qsf diff | blob | history
de1_nes/de1_nes.vhd diff | blob | history
de1_nes/mos6502-timing.sdc [new file with mode: 0644] blob
de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do diff | blob | history
de1_nes/testbench_motones_sim.vhd diff | blob | history
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