\r
#ifndef AT91SAM7S256_H\r
# define AT91SAM7S256_H\r
-\r
typedef volatile unsigned int AT91_REG; // Hardware register definition\r
\r
\r
// SOFTWARE API DEFINITION FOR System Peripherals\r
// *****************************************************************************\r
typedef struct _AT91S_SYS {\r
- \r
-AT91_REG AIC_SMR[32]; // Source Mode Register\r
+ AT91_REG AIC_SMR[32]; // Source Mode Register\r
AT91_REG AIC_SVR[32]; // Source Vector Register\r
AT91_REG AIC_IVR; // IRQ Vector Register\r
AT91_REG AIC_FVR; // FIQ Vector Register\r
} AT91S_SYS, *AT91PS_SYS;\r
\r
\r
-\r
-\r
// *****************************************************************************\r
// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller\r
// *****************************************************************************\r
typedef struct _AT91S_AIC {\r
- \r
-AT91_REG AIC_SMR[32]; // Source Mode Register\r
+ AT91_REG AIC_SMR[32]; // Source Mode Register\r
AT91_REG AIC_SVR[32]; // Source Vector Register\r
AT91_REG AIC_IVR; // IRQ Vector Register\r
AT91_REG AIC_FVR; // FIQ Vector Register\r
} AT91S_AIC, *AT91PS_AIC;\r
\r
\r
-\r
// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------\r
# define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level\r
# define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level\r
// SOFTWARE API DEFINITION FOR Peripheral DMA Controller\r
// *****************************************************************************\r
typedef struct _AT91S_PDC {\r
- \r
-AT91_REG PDC_RPR; // Receive Pointer Register\r
+ AT91_REG PDC_RPR; // Receive Pointer Register\r
AT91_REG PDC_RCR; // Receive Counter Register\r
AT91_REG PDC_TPR; // Transmit Pointer Register\r
AT91_REG PDC_TCR; // Transmit Counter Register\r
} AT91S_PDC, *AT91PS_PDC;\r
\r
\r
-\r
// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------\r
# define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable\r
# define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable\r
// SOFTWARE API DEFINITION FOR Debug Unit\r
// *****************************************************************************\r
typedef struct _AT91S_DBGU {\r
- \r
-AT91_REG DBGU_CR; // Control Register\r
+ AT91_REG DBGU_CR; // Control Register\r
AT91_REG DBGU_MR; // Mode Register\r
AT91_REG DBGU_IER; // Interrupt Enable Register\r
AT91_REG DBGU_IDR; // Interrupt Disable Register\r
} AT91S_DBGU, *AT91PS_DBGU;\r
\r
\r
-\r
// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------\r
# define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver\r
# define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter\r
// SOFTWARE API DEFINITION FOR Parallel Input Output Controler\r
// *****************************************************************************\r
typedef struct _AT91S_PIO {\r
- \r
-AT91_REG PIO_PER; // PIO Enable Register\r
+ AT91_REG PIO_PER; // PIO Enable Register\r
AT91_REG PIO_PDR; // PIO Disable Register\r
AT91_REG PIO_PSR; // PIO Status Register\r
AT91_REG Reserved0[1]; //\r
} AT91S_PIO, *AT91PS_PIO;\r
\r
\r
-\r
-\r
// *****************************************************************************\r
// SOFTWARE API DEFINITION FOR Clock Generator Controler\r
// *****************************************************************************\r
typedef struct _AT91S_CKGR {\r
- \r
-AT91_REG CKGR_MOR; // Main Oscillator Register\r
+ AT91_REG CKGR_MOR; // Main Oscillator Register\r
AT91_REG CKGR_MCFR; // Main Clock Frequency Register\r
AT91_REG Reserved0[1]; //\r
AT91_REG CKGR_PLLR; // PLL Register\r
} AT91S_CKGR, *AT91PS_CKGR;\r
\r
\r
-\r
// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------\r
# define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable\r
# define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass\r
// SOFTWARE API DEFINITION FOR Power Management Controler\r
// *****************************************************************************\r
typedef struct _AT91S_PMC {\r
- \r
-AT91_REG PMC_SCER; // System Clock Enable Register\r
+ AT91_REG PMC_SCER; // System Clock Enable Register\r
AT91_REG PMC_SCDR; // System Clock Disable Register\r
AT91_REG PMC_SCSR; // System Clock Status Register\r
AT91_REG Reserved0[1]; //\r
} AT91S_PMC, *AT91PS_PMC;\r
\r
\r
-\r
// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------\r
# define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock\r
# define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock\r
// SOFTWARE API DEFINITION FOR Reset Controller Interface\r
// *****************************************************************************\r
typedef struct _AT91S_RSTC {\r
- \r
-AT91_REG RSTC_RCR; // Reset Control Register\r
+ AT91_REG RSTC_RCR; // Reset Control Register\r
AT91_REG RSTC_RSR; // Reset Status Register\r
AT91_REG RSTC_RMR; // Reset Mode Register\r
} AT91S_RSTC, *AT91PS_RSTC;\r
\r
\r
-\r
// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------\r
# define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset\r
# define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset\r
// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface\r
// *****************************************************************************\r
typedef struct _AT91S_RTTC {\r
- \r
-AT91_REG RTTC_RTMR; // Real-time Mode Register\r
+ AT91_REG RTTC_RTMR; // Real-time Mode Register\r
AT91_REG RTTC_RTAR; // Real-time Alarm Register\r
AT91_REG RTTC_RTVR; // Real-time Value Register\r
AT91_REG RTTC_RTSR; // Real-time Status Register\r
} AT91S_RTTC, *AT91PS_RTTC;\r
\r
\r
-\r
// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------\r
# define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value\r
# define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable\r
// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface\r
// *****************************************************************************\r
typedef struct _AT91S_PITC {\r
- \r
-AT91_REG PITC_PIMR; // Period Interval Mode Register\r
+ AT91_REG PITC_PIMR; // Period Interval Mode Register\r
AT91_REG PITC_PISR; // Period Interval Status Register\r
AT91_REG PITC_PIVR; // Period Interval Value Register\r
AT91_REG PITC_PIIR; // Period Interval Image Register\r
} AT91S_PITC, *AT91PS_PITC;\r
\r
\r
-\r
// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------\r
# define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value\r
# define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled\r
// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface\r
// *****************************************************************************\r
typedef struct _AT91S_WDTC {\r
- \r
-AT91_REG WDTC_WDCR; // Watchdog Control Register\r
+ AT91_REG WDTC_WDCR; // Watchdog Control Register\r
AT91_REG WDTC_WDMR; // Watchdog Mode Register\r
AT91_REG WDTC_WDSR; // Watchdog Status Register\r
} AT91S_WDTC, *AT91PS_WDTC;\r
\r
\r
-\r
// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------\r
# define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart\r
# define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password\r
// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface\r
// *****************************************************************************\r
typedef struct _AT91S_VREG {\r
- \r
-AT91_REG VREG_MR; // Voltage Regulator Mode Register\r
+ AT91_REG VREG_MR; // Voltage Regulator Mode Register\r
} AT91S_VREG, *AT91PS_VREG;\r
\r
\r
-\r
// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------\r
# define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode\r
\r
// SOFTWARE API DEFINITION FOR Memory Controller Interface\r
// *****************************************************************************\r
typedef struct _AT91S_MC {\r
- \r
-AT91_REG MC_RCR; // MC Remap Control Register\r
+ AT91_REG MC_RCR; // MC Remap Control Register\r
AT91_REG MC_ASR; // MC Abort Status Register\r
AT91_REG MC_AASR; // MC Abort Address Status Register\r
AT91_REG Reserved0[21]; //\r
} AT91S_MC, *AT91PS_MC;\r
\r
\r
-\r
// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------\r
# define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit\r
// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------\r
// SOFTWARE API DEFINITION FOR Serial Parallel Interface\r
// *****************************************************************************\r
typedef struct _AT91S_SPI {\r
- \r
-AT91_REG SPI_CR; // Control Register\r
+ AT91_REG SPI_CR; // Control Register\r
AT91_REG SPI_MR; // Mode Register\r
AT91_REG SPI_RDR; // Receive Data Register\r
AT91_REG SPI_TDR; // Transmit Data Register\r
} AT91S_SPI, *AT91PS_SPI;\r
\r
\r
-\r
// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------\r
# define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable\r
# define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable\r
// SOFTWARE API DEFINITION FOR Analog to Digital Convertor\r
// *****************************************************************************\r
typedef struct _AT91S_ADC {\r
- \r
-AT91_REG ADC_CR; // ADC Control Register\r
+ AT91_REG ADC_CR; // ADC Control Register\r
AT91_REG ADC_MR; // ADC Mode Register\r
AT91_REG Reserved0[2]; //\r
AT91_REG ADC_CHER; // ADC Channel Enable Register\r
} AT91S_ADC, *AT91PS_ADC;\r
\r
\r
-\r
// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------\r
# define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset\r
# define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion\r
// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface\r
// *****************************************************************************\r
typedef struct _AT91S_SSC {\r
- \r
-AT91_REG SSC_CR; // Control Register\r
+ AT91_REG SSC_CR; // Control Register\r
AT91_REG SSC_CMR; // Clock Mode Register\r
AT91_REG Reserved0[2]; //\r
AT91_REG SSC_RCMR; // Receive Clock ModeRegister\r
} AT91S_SSC, *AT91PS_SSC;\r
\r
\r
-\r
// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------\r
# define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable\r
# define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable\r
// SOFTWARE API DEFINITION FOR Usart\r
// *****************************************************************************\r
typedef struct _AT91S_USART {\r
- \r
-AT91_REG US_CR; // Control Register\r
+ AT91_REG US_CR; // Control Register\r
AT91_REG US_MR; // Mode Register\r
AT91_REG US_IER; // Interrupt Enable Register\r
AT91_REG US_IDR; // Interrupt Disable Register\r
} AT91S_USART, *AT91PS_USART;\r
\r
\r
-\r
// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------\r
# define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break\r
# define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break\r
// SOFTWARE API DEFINITION FOR Two-wire Interface\r
// *****************************************************************************\r
typedef struct _AT91S_TWI {\r
- \r
-AT91_REG TWI_CR; // Control Register\r
+ AT91_REG TWI_CR; // Control Register\r
AT91_REG TWI_MMR; // Master Mode Register\r
AT91_REG Reserved0[1]; //\r
AT91_REG TWI_IADR; // Internal Address Register\r
} AT91S_TWI, *AT91PS_TWI;\r
\r
\r
-\r
// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------\r
# define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition\r
# define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition\r
// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface\r
// *****************************************************************************\r
typedef struct _AT91S_TC {\r
- \r
-AT91_REG TC_CCR; // Channel Control Register\r
+ AT91_REG TC_CCR; // Channel Control Register\r
AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)\r
AT91_REG Reserved0[2]; //\r
AT91_REG TC_CV; // Counter Value\r
} AT91S_TC, *AT91PS_TC;\r
\r
\r
-\r
// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------\r
# define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command\r
# define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command\r
// SOFTWARE API DEFINITION FOR Timer Counter Interface\r
// *****************************************************************************\r
typedef struct _AT91S_TCB {\r
- \r
-AT91S_TC TCB_TC0; // TC Channel 0\r
+ AT91S_TC TCB_TC0; // TC Channel 0\r
AT91_REG Reserved0[4]; //\r
AT91S_TC TCB_TC1; // TC Channel 1\r
AT91_REG Reserved1[4]; //\r
} AT91S_TCB, *AT91PS_TCB;\r
\r
\r
-\r
// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------\r
# define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command\r
// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------\r
// SOFTWARE API DEFINITION FOR PWMC Channel Interface\r
// *****************************************************************************\r
typedef struct _AT91S_PWMC_CH {\r
- \r
-AT91_REG PWMC_CMR; // Channel Mode Register\r
+ AT91_REG PWMC_CMR; // Channel Mode Register\r
AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register\r
AT91_REG PWMC_CPRDR; // Channel Period Register\r
AT91_REG PWMC_CCNTR; // Channel Counter Register\r
} AT91S_PWMC_CH, *AT91PS_PWMC_CH;\r
\r
\r
-\r
// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------\r
# define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx\r
# define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH)\r
// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface\r
// *****************************************************************************\r
typedef struct _AT91S_PWMC {\r
- \r
-AT91_REG PWMC_MR; // PWMC Mode Register\r
+ AT91_REG PWMC_MR; // PWMC Mode Register\r
AT91_REG PWMC_ENA; // PWMC Enable Register\r
AT91_REG PWMC_DIS; // PWMC Disable Register\r
AT91_REG PWMC_SR; // PWMC Status Register\r
} AT91S_PWMC, *AT91PS_PWMC;\r
\r
\r
-\r
// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------\r
# define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor.\r
# define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A\r
// SOFTWARE API DEFINITION FOR USB Device Interface\r
// *****************************************************************************\r
typedef struct _AT91S_UDP {\r
- \r
-AT91_REG UDP_NUM; // Frame Number Register\r
+ AT91_REG UDP_NUM; // Frame Number Register\r
AT91_REG UDP_GLBSTATE; // Global State Register\r
AT91_REG UDP_FADDR; // Function Address Register\r
AT91_REG Reserved0[1]; //\r
} AT91S_UDP, *AT91PS_UDP;\r
\r
\r
-\r
// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------\r
# define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats\r
# define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error\r
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