+++ /dev/null
-/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Oct 15 11:16:52 2011\r
- Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER:\r
-*/\r
-\r
-module SDRAMC ( p_reset , m_clock , o_ADRS , o_BA , io_DQ , o_RAS , o_CAS , o_WE , io_DQM , o_tLED );\r
- input p_reset;\r
- input m_clock;\r
- output [11:0] o_ADRS;\r
- output [1:0] o_BA;\r
-inout [15:0] io_DQ;\r
- output o_RAS;\r
- output o_CAS;\r
- output o_WE;\r
-inout [1:0] io_DQM;\r
- output o_tLED;\r
- wire [13:0] w_adrs;\r
- wire [15:0] w_wdata;\r
- wire [15:0] w_rdata;\r
- reg [26:0] r_tLED_cnt;\r
- reg r_tLED;\r
- wire fs_refresh;\r
- wire fs_SingleWrite;\r
- wire fs_SingleRead;\r
- wire fs_BurstWrite;\r
- wire fs_BurstRead;\r
- wire _net_0;\r
- wire _net_1;\r
-\r
- assign fs_refresh = 1'b0;\r
- assign fs_SingleWrite = 1'b0;\r
- assign fs_SingleRead = 1'b0;\r
- assign fs_BurstWrite = 1'b0;\r
- assign fs_BurstRead = 1'b0;\r
- assign _net_0 = (r_tLED_cnt)==(27'b101111101011110000100000000);\r
- assign _net_1 = ~_net_0;\r
- assign o_tLED = r_tLED;\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- r_tLED_cnt <= 27'b000000000000000000000000000;\r
-else if ((_net_1)|(_net_0)) \r
- r_tLED_cnt <= ((_net_1) ?(r_tLED_cnt)+(27'b000000000000000000000000001):27'b0)|\r
- ((_net_0) ?27'b000000000000000000000000000:27'b0);\r
-\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- r_tLED <= 1'b0;\r
-else if ((_net_0)) \r
- r_tLED <= ~r_tLED;\r
-end\r
-endmodule\r
-/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Oct 15 11:16:53 2011\r
- Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
-*/\r
-\r
-module btn_ctrl ( p_reset , m_clock , i_sw , fo_sw_enb );\r
- input p_reset, m_clock;\r
- input i_sw;\r
- output fo_sw_enb;\r
- reg [18:0] r_cnt;\r
- reg r_rise_flag;\r
- reg r_sw_hld;\r
- reg r_finish_flag;\r
- wire _net_2;\r
- wire _net_3;\r
- wire _net_4;\r
- wire _net_5;\r
- wire _net_6;\r
- wire _net_7;\r
- wire _net_8;\r
- wire _net_9;\r
- wire _net_10;\r
- wire _net_11;\r
- wire _net_12;\r
-\r
- assign _net_2 = i_sw&(~r_sw_hld);\r
- assign _net_3 = ~i_sw;\r
- assign _net_4 = ~_net_2;\r
- assign _net_5 = (~_net_2)&_net_3;\r
- assign _net_6 = (~_net_2)&_net_3;\r
- assign _net_7 = (r_rise_flag)==(1'b1);\r
- assign _net_8 = ((r_cnt)==(19'b1111010000100100000))&((r_finish_flag)==(1'b0));\r
- assign _net_9 = _net_7&_net_8;\r
- assign _net_10 = _net_7&_net_8;\r
- assign _net_11 = _net_7&(~_net_8);\r
- assign _net_12 = ~_net_7;\r
- assign fo_sw_enb = _net_10;\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- r_cnt <= 19'b0000000000000000000;\r
-else if ((_net_12)|(_net_11)) \r
- r_cnt <= ((_net_12) ?26'b00000000000000000000000000:19'b0)|\r
- ((_net_11) ?(r_cnt)+(19'b0000000000000000001):19'b0);\r
-\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- r_rise_flag <= 1'b0;\r
-else if ((_net_5)|(_net_2)) \r
- r_rise_flag <= ((_net_5) ?1'b0:1'b0)|\r
- ((_net_2) ?1'b1:1'b0);\r
-\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- r_sw_hld <= 1'b0;\r
-else r_sw_hld <= i_sw;\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- r_finish_flag <= 1'b0;\r
-else if ((_net_9)|(_net_6)) \r
- r_finish_flag <= ((_net_9) ?1'b1:1'b0)|\r
- ((_net_6) ?1'b0:1'b0);\r
-\r
-end\r
-endmodule\r
-/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Oct 15 11:16:55 2011\r
- Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
-*/\r
-\r
-module SDRAM_top ( p_reset , m_clock , o_ADRS , o_BA , io_DQ , o_CS , o_RAS , o_CAS , o_WE , io_DQM , o_CLK100 , o_tLED , o_tLED2 , o_locked );\r
- input p_reset, m_clock;\r
- output [11:0] o_ADRS;\r
- output [1:0] o_BA;\r
-inout [15:0] io_DQ;\r
- output o_CS;\r
- output o_RAS;\r
- output o_CAS;\r
- output o_WE;\r
-inout [1:0] io_DQM;\r
- output o_CLK100;\r
- output o_tLED;\r
- output o_tLED2;\r
- output o_locked;\r
- reg [25:0] cnt;\r
- reg tLED2;\r
- wire _u_SDRAMC_p_reset;\r
- wire _u_SDRAMC_m_clock;\r
- wire [11:0] _u_SDRAMC_o_ADRS;\r
- wire [1:0] _u_SDRAMC_o_BA;\r
- wire [15:0] _u_SDRAMC_io_DQ;\r
- wire _u_SDRAMC_o_RAS;\r
- wire _u_SDRAMC_o_CAS;\r
- wire _u_SDRAMC_o_WE;\r
- wire [1:0] _u_SDRAMC_io_DQM;\r
- wire _u_SDRAMC_o_tLED;\r
- wire _u_BTN_i_sw;\r
- wire _u_BTN_fo_sw_enb;\r
- wire _u_BTN_p_reset;\r
- wire _u_BTN_m_clock;\r
- wire _u_PLL_areset;\r
- wire _u_PLL_inclk0;\r
- wire _u_PLL_c0;\r
- wire _u_PLL_locked;\r
- wire _net_13;\r
- wire _net_14;\r
-PLLU u_PLL (.locked(_u_PLL_locked), .c0(_u_PLL_c0), .inclk0(_u_PLL_inclk0), .areset(_u_PLL_areset));\r
-btn_ctrl u_BTN (.p_reset(p_reset), .m_clock(m_clock), .fo_sw_enb(_u_BTN_fo_sw_enb), .i_sw(_u_BTN_i_sw));\r
-SDRAMC u_SDRAMC (.o_tLED(_u_SDRAMC_o_tLED), .io_DQM(_u_SDRAMC_io_DQM), .o_WE(_u_SDRAMC_o_WE), .o_CAS(_u_SDRAMC_o_CAS), .o_RAS(_u_SDRAMC_o_RAS), .io_DQ(_u_SDRAMC_io_DQ), .o_BA(_u_SDRAMC_o_BA), .o_ADRS(_u_SDRAMC_o_ADRS), .m_clock(_u_SDRAMC_m_clock), .p_reset(_u_SDRAMC_p_reset));\r
-\r
- assign _u_SDRAMC_p_reset = 1'b0;\r
- assign _u_SDRAMC_m_clock = _u_PLL_c0;\r
- assign _u_PLL_areset = 1'b0;\r
- assign _u_PLL_inclk0 = m_clock;\r
- assign _net_13 = (cnt)==(50'b00000000000000000000000010111110101111000010000000);\r
- assign _net_14 = ~_net_13;\r
- assign o_tLED = _u_SDRAMC_o_tLED;\r
- assign o_tLED2 = tLED2;\r
- assign o_locked = _u_PLL_locked;\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- cnt <= 26'b00000000000000000000000000;\r
-else if ((_net_14)|(_net_13)) \r
- cnt <= ((_net_14) ?(cnt)+(26'b00000000000000000000000001):26'b0)|\r
- ((_net_13) ?26'b00000000000000000000000000:26'b0);\r
-\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- tLED2 <= 1'b0;\r
-else if ((_net_13)) \r
- tLED2 <= ~tLED2;\r
-end\r
-endmodule\r
-/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Oct 15 11:16:56 2011\r
- Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
-*/\r
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