/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Nov 19 16:48:34 2011\r
- Licensed to :LIMITED EVALUATION USER:\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Sun Jan 08 12:30:56 2012\r
+ Licensed to Yujiro_Kaneko::zyangalianhamster01@gmail.com :NON PROFIT USER:\r
*/\r
\r
module vga_gen ( i_clk50 , i_fifo_rst , m_clock , p_reset , o_vsync , o_hsync , o_vga_r , o_vga_g , o_vga_b , o_dummy_rgb , o_vcnt , i_wrdata , fi_fifo_write , o_rdack , o_led );\r
reg _reg_59;\r
reg _reg_60;\r
reg _reg_61;\r
- reg _reg_62;\r
+ wire _net_62;\r
wire _net_63;\r
wire _net_64;\r
wire _net_65;\r
- wire _net_66;\r
- wire _net_67;\r
- reg _reg_68;\r
- reg _reg_69;\r
- wire _net_70;\r
+ reg _reg_66;\r
+ reg _reg_67;\r
+ wire _net_68;\r
vga_ram u_FIFO (.o_rdack(_u_FIFO_o_rdack), .o_rddata(_u_FIFO_o_rddata), .i_re(_u_FIFO_i_re), .i_wrdata(_u_FIFO_i_wrdata), .i_we(_u_FIFO_i_we), .i_clk25(_u_FIFO_i_clk25), .i_clk50(_u_FIFO_i_clk50), .i_rst(_u_FIFO_i_rst));\r
\r
- assign fs_fifo_read = _net_63|_reg_60|_net_15;\r
+ assign fs_fifo_read = _reg_60|_net_15;\r
assign w_rddata = _u_FIFO_o_rddata;\r
- assign fs_fifo_ack = _reg_68;\r
+ assign fs_fifo_ack = _reg_66;\r
assign fs_initialize = _net_0;\r
assign _u_FIFO_i_rst = i_fifo_rst;\r
assign _u_FIFO_i_clk50 = i_clk50;\r
assign _net_55 = (r_vcnt)==(10'b0111101011);\r
assign _net_56 = (r_vcnt)==(10'b0111101001);\r
assign _net_57 = (r_vcnt)==(10'b0111100000);\r
- assign _net_63 = fs_initialize|_reg_62;\r
- assign _net_64 = fs_initialize|_reg_61|_reg_62;\r
- assign _net_65 = fs_initialize|_reg_60|_reg_61;\r
- assign _net_66 = fs_initialize|_reg_59|_reg_60;\r
- assign _net_67 = fs_initialize|_reg_58|_reg_59;\r
- assign _net_70 = fs_fifo_read|_reg_68|_reg_69;\r
+ assign _net_62 = fs_initialize|_reg_61;\r
+ assign _net_63 = fs_initialize|_reg_60|_reg_61;\r
+ assign _net_64 = fs_initialize|_reg_59|_reg_60;\r
+ assign _net_65 = fs_initialize|_reg_58|_reg_59;\r
+ assign _net_68 = fs_fifo_read|_reg_66|_reg_67;\r
assign o_vsync = r_vsync;\r
assign o_hsync = r_hsync;\r
assign o_vga_r = ((_net_45|_net_33)?4'b0000:4'b0)|\r
begin\r
if (p_reset)\r
r_data1 <= 8'b00000000;\r
-else if ((_reg_61)|(_net_51|_net_16)) \r
- r_data1 <= ((_reg_61) ?_u_FIFO_o_rddata:8'b0)|\r
+else if ((_net_62)|(_net_51|_net_16)) \r
+ r_data1 <= ((_net_62) ?_u_FIFO_o_rddata:8'b0)|\r
((_net_51|_net_16) ?w_rddata:8'b0);\r
\r
end\r
begin\r
if (p_reset)\r
_reg_58 <= 1'b0;\r
-else if ((_net_67)) \r
+else if ((_net_65)) \r
_reg_58 <= _reg_59;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
_reg_59 <= 1'b0;\r
-else if ((_net_66)) \r
+else if ((_net_64)) \r
_reg_59 <= _reg_60;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
_reg_60 <= 1'b0;\r
-else if ((_net_65)) \r
- _reg_60 <= _reg_61;\r
+else if ((_net_63)) \r
+ _reg_60 <= _reg_61|fs_initialize;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
_reg_61 <= 1'b0;\r
-else if ((_net_64)) \r
- _reg_61 <= _reg_62|fs_initialize;\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- _reg_62 <= 1'b0;\r
-else if ((_reg_62)) \r
- _reg_62 <= 1'b0;\r
+else if ((_reg_61)) \r
+ _reg_61 <= 1'b0;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_68 <= 1'b0;\r
-else if ((_net_70)) \r
- _reg_68 <= _reg_69|fs_fifo_read;\r
+ _reg_66 <= 1'b0;\r
+else if ((_net_68)) \r
+ _reg_66 <= _reg_67|fs_fifo_read;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_69 <= 1'b0;\r
-else if ((_reg_69)) \r
- _reg_69 <= 1'b0;\r
+ _reg_67 <= 1'b0;\r
+else if ((_reg_67)) \r
+ _reg_67 <= 1'b0;\r
end\r
endmodule\r
/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Nov 19 16:48:39 2011\r
- Licensed to :LIMITED EVALUATION USER:\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Sun Jan 08 12:31:01 2012\r
+ Licensed to Yujiro_Kaneko::zyangalianhamster01@gmail.com \r
*/\r