/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Wed Aug 10 20:43:42 2011\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Aug 20 23:09:32 2011\r
Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER:\r
*/\r
\r
-module vga_gen ( i_clk50M , m_clock , p_reset , o_vsync , o_hsync , o_vga_r , o_vga_g , o_vga_b , i_wrdata1 , i_wrdata2 , fi_fifo1_write , fi_fifo2_write , fi_fifo1_reset , fi_fifo2_reset , outled , o_vcnt );\r
+module vga_gen ( i_clk50M , m_clock , p_reset , o_vsync , o_hsync , o_vga_r , o_vga_g , o_vga_b , i_wrdata1 , i_wrdata2 , i_wradrs1 , i_wradrs2 , fi_fifo1_write , fi_fifo2_write , outled , o_vcnt );\r
input i_clk50M;\r
input m_clock;\r
input p_reset;\r
output [3:0] o_vga_b;\r
input [7:0] i_wrdata1;\r
input [7:0] i_wrdata2;\r
+ input [7:0] i_wradrs1;\r
+ input [7:0] i_wradrs2;\r
input fi_fifo1_write;\r
input fi_fifo2_write;\r
- input fi_fifo1_reset;\r
- input fi_fifo2_reset;\r
output outled;\r
output [9:0] o_vcnt;\r
wire fs_fifo1_read;\r
wire fs_fifo2_read;\r
wire fs_fifo1_exec;\r
wire fs_fifo2_exec;\r
+ wire fs_fifo1_reset;\r
+ wire fs_fifo2_reset;\r
reg [4:0] r_bit_number;\r
reg r_vsync;\r
reg r_hsync;\r
reg testled;\r
reg [2:0] r_outcnt;\r
reg [6:0] r_outclr;\r
+ reg r_vcnt_hld;\r
wire [23:0] w_rddata1;\r
wire [23:0] w_rddata2;\r
+ reg [7:0] r_rdadrs1;\r
+ reg [7:0] r_rdadrs2;\r
wire _u_FIFO_p_reset;\r
wire _u_FIFO_m_clock;\r
wire _u_FIFO_i_we1;\r
- wire [7:0] _u_FIFO_i_wdata1;\r
+ wire [7:0] _u_FIFO_i_wrdata1;\r
+ wire [7:0] _u_FIFO_i_wradrs1;\r
wire _u_FIFO_i_we2;\r
- wire [7:0] _u_FIFO_i_wdata2;\r
+ wire [7:0] _u_FIFO_i_wrdata2;\r
+ wire [7:0] _u_FIFO_i_wradrs2;\r
wire [23:0] _u_FIFO_o_rddata1;\r
wire [23:0] _u_FIFO_o_rddata2;\r
+ wire [7:0] _u_FIFO_i_rdadrs1;\r
+ wire [7:0] _u_FIFO_i_rdadrs2;\r
wire _u_FIFO_i_clock;\r
wire _u_FIFO_i_re1;\r
wire _u_FIFO_i_re2;\r
- wire _u_FIFO_i_fifo1_rst;\r
- wire _u_FIFO_i_fifo2_rst;\r
wire _u_FIFO_o_rdack1;\r
wire _u_FIFO_o_rdack2;\r
wire _net_0;\r
wire _net_50;\r
wire _net_51;\r
wire _net_52;\r
-vga_ram u_FIFO (.o_rdack2(_u_FIFO_o_rdack2), .o_rdack1(_u_FIFO_o_rdack1), .i_fifo2_rst(_u_FIFO_i_fifo2_rst), .i_fifo1_rst(_u_FIFO_i_fifo1_rst), .i_re2(_u_FIFO_i_re2), .i_re1(_u_FIFO_i_re1), .i_clock(_u_FIFO_i_clock), .o_rddata2(_u_FIFO_o_rddata2), .o_rddata1(_u_FIFO_o_rddata1), .i_wdata2(_u_FIFO_i_wdata2), .i_we2(_u_FIFO_i_we2), .i_wdata1(_u_FIFO_i_wdata1), .i_we1(_u_FIFO_i_we1), .m_clock(_u_FIFO_m_clock), .p_reset(_u_FIFO_p_reset));\r
+ wire _net_53;\r
+ wire _net_54;\r
+vga_ram u_FIFO (.o_rdack2(_u_FIFO_o_rdack2), .o_rdack1(_u_FIFO_o_rdack1), .i_re2(_u_FIFO_i_re2), .i_re1(_u_FIFO_i_re1), .i_clock(_u_FIFO_i_clock), .i_rdadrs2(_u_FIFO_i_rdadrs2), .i_rdadrs1(_u_FIFO_i_rdadrs1), .o_rddata2(_u_FIFO_o_rddata2), .o_rddata1(_u_FIFO_o_rddata1), .i_wradrs2(_u_FIFO_i_wradrs2), .i_wrdata2(_u_FIFO_i_wrdata2), .i_we2(_u_FIFO_i_we2), .i_wradrs1(_u_FIFO_i_wradrs1), .i_wrdata1(_u_FIFO_i_wrdata1), .i_we1(_u_FIFO_i_we1), .m_clock(_u_FIFO_m_clock), .p_reset(_u_FIFO_p_reset));\r
\r
- assign fs_fifo1_read = _net_20;\r
- assign fs_fifo2_read = _net_17;\r
- assign fs_fifo1_exec = _net_12;\r
- assign fs_fifo2_exec = _net_10;\r
+ assign fs_fifo1_read = _net_22;\r
+ assign fs_fifo2_read = _net_19;\r
+ assign fs_fifo1_exec = _net_14;\r
+ assign fs_fifo2_exec = _net_12;\r
+ assign fs_fifo1_reset = _net_1;\r
+ assign fs_fifo2_reset = _net_0;\r
assign w_rddata1 = _u_FIFO_o_rddata1;\r
assign w_rddata2 = _u_FIFO_o_rddata2;\r
assign _u_FIFO_m_clock = m_clock;\r
assign _u_FIFO_i_we1 = fi_fifo1_write;\r
- assign _u_FIFO_i_wdata1 = i_wrdata1;\r
+ assign _u_FIFO_i_wrdata1 = i_wrdata1;\r
+ assign _u_FIFO_i_wradrs1 = i_wradrs1;\r
assign _u_FIFO_i_we2 = fi_fifo2_write;\r
- assign _u_FIFO_i_wdata2 = i_wrdata2;\r
+ assign _u_FIFO_i_wrdata2 = i_wrdata2;\r
+ assign _u_FIFO_i_wradrs2 = i_wradrs2;\r
+ assign _u_FIFO_i_rdadrs1 = r_rdadrs1;\r
+ assign _u_FIFO_i_rdadrs2 = r_rdadrs2;\r
assign _u_FIFO_i_clock = i_clk50M;\r
assign _u_FIFO_i_re1 = fs_fifo1_read;\r
assign _u_FIFO_i_re2 = fs_fifo2_read;\r
- assign _u_FIFO_i_fifo1_rst = fi_fifo1_reset;\r
- assign _u_FIFO_i_fifo2_rst = fi_fifo2_reset;\r
- assign _net_0 = (cnt)==(26'b01011111010111100001000000);\r
- assign _net_1 = ~_net_0;\r
- assign _net_2 = (r_hcnt) < (10'b1100100000);\r
+ assign _net_0 = r_vcnt_hld&(~(r_vcnt[0]));\r
+ assign _net_1 = (~r_vcnt_hld)&(r_vcnt[0]);\r
+ assign _net_2 = (cnt)==(26'b01011111010111100001000000);\r
assign _net_3 = ~_net_2;\r
- assign _net_4 = (r_vcnt) < (10'b1000001001);\r
- assign _net_5 = ~_net_2;\r
- assign _net_6 = (~_net_2)&_net_4;\r
- assign _net_7 = (~_net_2)&(~_net_4);\r
- assign _net_8 = ((r_hcnt) < (10'b1010000000))&((r_vcnt) < (10'b0111100000));\r
- assign _net_9 = r_vcnt[0];\r
- assign _net_10 = _net_8&_net_9;\r
- assign _net_11 = ~(r_vcnt[0]);\r
- assign _net_12 = _net_8&_net_11;\r
- assign _net_13 = (r_bit_number)==(5'b10111);\r
- assign _net_14 = _net_8&_net_13;\r
- assign _net_15 = r_vcnt[0];\r
- assign _net_16 = _net_8&_net_13;\r
- assign _net_17 = (_net_8&_net_13)&_net_15;\r
- assign _net_18 = ~(r_vcnt[0]);\r
- assign _net_19 = _net_8&_net_13;\r
- assign _net_20 = (_net_8&_net_13)&_net_18;\r
- assign _net_21 = _net_8&(~_net_13);\r
- assign _net_22 = (r_hcnt)==(10'b1011110000);\r
- assign _net_23 = ~_net_8;\r
- assign _net_24 = (~_net_8)&_net_22;\r
- assign _net_25 = (r_hcnt)==(10'b1010010000);\r
- assign _net_26 = ~_net_8;\r
- assign _net_27 = (~_net_8)&_net_25;\r
- assign _net_28 = (r_hcnt)==(10'b1010000000);\r
- assign _net_29 = ~_net_8;\r
- assign _net_30 = (~_net_8)&_net_28;\r
- assign _net_31 = (~_net_8)&_net_28;\r
- assign _net_32 = (~_net_8)&_net_28;\r
- assign _net_33 = (~_net_8)&_net_28;\r
- assign _net_34 = (~_net_8)&_net_28;\r
- assign _net_35 = (~_net_8)&_net_28;\r
- assign _net_36 = (r_vcnt)==(10'b0111101100);\r
- assign _net_37 = (r_vcnt)==(10'b0111101010);\r
- assign _net_38 = (r_vcnt)==(10'b0111100000);\r
- assign _net_39 = w_rddata1[r_bit_number];\r
- assign _net_40 = fs_fifo1_exec&_net_39;\r
- assign _net_41 = fs_fifo1_exec&_net_39;\r
- assign _net_42 = fs_fifo1_exec&_net_39;\r
- assign _net_43 = fs_fifo1_exec&(~_net_39);\r
- assign _net_44 = fs_fifo1_exec&(~_net_39);\r
- assign _net_45 = fs_fifo1_exec&(~_net_39);\r
- assign _net_46 = w_rddata2[r_bit_number];\r
- assign _net_47 = fs_fifo2_exec&_net_46;\r
- assign _net_48 = fs_fifo2_exec&_net_46;\r
- assign _net_49 = fs_fifo2_exec&_net_46;\r
- assign _net_50 = fs_fifo2_exec&(~_net_46);\r
- assign _net_51 = fs_fifo2_exec&(~_net_46);\r
- assign _net_52 = fs_fifo2_exec&(~_net_46);\r
+ assign _net_4 = (r_hcnt) < (10'b1100100000);\r
+ assign _net_5 = ~_net_4;\r
+ assign _net_6 = (r_vcnt) < (10'b1000001001);\r
+ assign _net_7 = ~_net_4;\r
+ assign _net_8 = (~_net_4)&_net_6;\r
+ assign _net_9 = (~_net_4)&(~_net_6);\r
+ assign _net_10 = ((r_hcnt) < (10'b1010000000))&((r_vcnt) < (10'b0111100000));\r
+ assign _net_11 = r_vcnt[0];\r
+ assign _net_12 = _net_10&_net_11;\r
+ assign _net_13 = ~(r_vcnt[0]);\r
+ assign _net_14 = _net_10&_net_13;\r
+ assign _net_15 = (r_bit_number)==(5'b10111);\r
+ assign _net_16 = _net_10&_net_15;\r
+ assign _net_17 = r_vcnt[0];\r
+ assign _net_18 = _net_10&_net_15;\r
+ assign _net_19 = (_net_10&_net_15)&_net_17;\r
+ assign _net_20 = ~(r_vcnt[0]);\r
+ assign _net_21 = _net_10&_net_15;\r
+ assign _net_22 = (_net_10&_net_15)&_net_20;\r
+ assign _net_23 = _net_10&(~_net_15);\r
+ assign _net_24 = (r_hcnt)==(10'b1011110000);\r
+ assign _net_25 = ~_net_10;\r
+ assign _net_26 = (~_net_10)&_net_24;\r
+ assign _net_27 = (r_hcnt)==(10'b1010010000);\r
+ assign _net_28 = ~_net_10;\r
+ assign _net_29 = (~_net_10)&_net_27;\r
+ assign _net_30 = (r_hcnt)==(10'b1010000000);\r
+ assign _net_31 = ~_net_10;\r
+ assign _net_32 = (~_net_10)&_net_30;\r
+ assign _net_33 = (~_net_10)&_net_30;\r
+ assign _net_34 = (~_net_10)&_net_30;\r
+ assign _net_35 = (~_net_10)&_net_30;\r
+ assign _net_36 = (~_net_10)&_net_30;\r
+ assign _net_37 = (~_net_10)&_net_30;\r
+ assign _net_38 = (r_vcnt)==(10'b0111101100);\r
+ assign _net_39 = (r_vcnt)==(10'b0111101010);\r
+ assign _net_40 = (r_vcnt)==(10'b0111100000);\r
+ assign _net_41 = w_rddata1[r_bit_number];\r
+ assign _net_42 = fs_fifo1_exec&_net_41;\r
+ assign _net_43 = fs_fifo1_exec&_net_41;\r
+ assign _net_44 = fs_fifo1_exec&_net_41;\r
+ assign _net_45 = fs_fifo1_exec&(~_net_41);\r
+ assign _net_46 = fs_fifo1_exec&(~_net_41);\r
+ assign _net_47 = fs_fifo1_exec&(~_net_41);\r
+ assign _net_48 = w_rddata2[r_bit_number];\r
+ assign _net_49 = fs_fifo2_exec&_net_48;\r
+ assign _net_50 = fs_fifo2_exec&_net_48;\r
+ assign _net_51 = fs_fifo2_exec&_net_48;\r
+ assign _net_52 = fs_fifo2_exec&(~_net_48);\r
+ assign _net_53 = fs_fifo2_exec&(~_net_48);\r
+ assign _net_54 = fs_fifo2_exec&(~_net_48);\r
assign o_vsync = r_vsync;\r
assign o_hsync = r_hsync;\r
- assign o_vga_r = ((_net_47|_net_40)?4'b1111:4'b0)|\r
- ((_net_50|_net_43|_net_30)?4'b0000:4'b0);\r
- assign o_vga_g = ((_net_48|_net_41)?4'b1111:4'b0)|\r
- ((_net_51|_net_44|_net_31)?4'b0000:4'b0);\r
- assign o_vga_b = ((_net_49|_net_42)?4'b1111:4'b0)|\r
+ assign o_vga_r = ((_net_49|_net_42)?4'b1111:4'b0)|\r
((_net_52|_net_45|_net_32)?4'b0000:4'b0);\r
+ assign o_vga_g = ((_net_50|_net_43)?4'b1111:4'b0)|\r
+ ((_net_53|_net_46|_net_33)?4'b0000:4'b0);\r
+ assign o_vga_b = ((_net_51|_net_44)?4'b1111:4'b0)|\r
+ ((_net_54|_net_47|_net_34)?4'b0000:4'b0);\r
assign outled = testled;\r
assign o_vcnt = r_vcnt;\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
r_bit_number <= 5'b00000;\r
-else if ((_net_21)|(_net_35|_net_14)) \r
- r_bit_number <= ((_net_21) ?(r_bit_number)+(5'b00001):5'b0)|\r
- ((_net_35|_net_14) ?5'b00000:5'b0);\r
+else if ((_net_23)|(_net_37|_net_16)) \r
+ r_bit_number <= ((_net_23) ?(r_bit_number)+(5'b00001):5'b0)|\r
+ ((_net_37|_net_16) ?5'b00000:5'b0);\r
\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
r_vsync <= 1'b0;\r
-else if ((_net_37)|(_net_36)) \r
- r_vsync <= ((_net_37) ?1'b0:1'b0)|\r
- ((_net_36) ?1'b1:1'b0);\r
+else if ((_net_39)|(_net_38)) \r
+ r_vsync <= ((_net_39) ?1'b0:1'b0)|\r
+ ((_net_38) ?1'b1:1'b0);\r
\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
r_hsync <= 1'b0;\r
-else if ((_net_27)|(_net_24)) \r
- r_hsync <= ((_net_27) ?1'b0:1'b0)|\r
- ((_net_24) ?1'b1:1'b0);\r
+else if ((_net_29)|(_net_26)) \r
+ r_hsync <= ((_net_29) ?1'b0:1'b0)|\r
+ ((_net_26) ?1'b1:1'b0);\r
\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
r_vcnt <= 10'b0000000000;\r
-else if ((_net_7)|(_net_6)) \r
- r_vcnt <= ((_net_7) ?10'b0000000000:10'b0)|\r
- ((_net_6) ?(r_vcnt)+(10'b0000000001):10'b0);\r
+else if ((_net_9)|(_net_8)) \r
+ r_vcnt <= ((_net_9) ?10'b0000000000:10'b0)|\r
+ ((_net_8) ?(r_vcnt)+(10'b0000000001):10'b0);\r
\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
r_hcnt <= 10'b0000000000;\r
-else if ((_net_3)|(_net_2)) \r
- r_hcnt <= ((_net_3) ?10'b0000000000:10'b0)|\r
- ((_net_2) ?(r_hcnt)+(10'b0000000001):10'b0);\r
+else if ((_net_5)|(_net_4)) \r
+ r_hcnt <= ((_net_5) ?10'b0000000000:10'b0)|\r
+ ((_net_4) ?(r_hcnt)+(10'b0000000001):10'b0);\r
\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
cnt <= 26'b00000000000000000000000000;\r
-else if ((_net_1)|(_net_0)) \r
- cnt <= ((_net_1) ?(cnt)+(26'b00000000000000000000000001):26'b0)|\r
- ((_net_0) ?26'b00000000000000000000000000:26'b0);\r
+else if ((_net_3)|(_net_2)) \r
+ cnt <= ((_net_3) ?(cnt)+(26'b00000000000000000000000001):26'b0)|\r
+ ((_net_2) ?26'b00000000000000000000000000:26'b0);\r
\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
testled <= 1'b0;\r
-else if ((_net_0)) \r
+else if ((_net_2)) \r
testled <= ~testled;\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
r_outcnt <= 3'b000;\r
-else if ((_net_33)) \r
+else if ((_net_35)) \r
r_outcnt <= 3'b000;\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
r_outclr <= 7'b0000000;\r
-else if ((_net_34)) \r
+else if ((_net_36)) \r
r_outclr <= 7'b0000000;\r
end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ r_vcnt_hld <= 1'b0;\r
+else r_vcnt_hld <= r_vcnt[0];\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ r_rdadrs1 <= 8'b00000000;\r
+else if ((fs_fifo1_reset)|(fs_fifo1_read)) \r
+ r_rdadrs1 <= ((fs_fifo1_reset) ?8'b00000000:8'b0)|\r
+ ((fs_fifo1_read) ?(r_rdadrs1)+(8'b00000011):8'b0);\r
+\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ r_rdadrs2 <= 8'b00000000;\r
+else if ((fs_fifo2_reset)|(fs_fifo2_read)) \r
+ r_rdadrs2 <= ((fs_fifo2_reset) ?8'b00000000:8'b0)|\r
+ ((fs_fifo2_read) ?(r_rdadrs2)+(8'b00000011):8'b0);\r
+\r
+end\r
endmodule\r
/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Wed Aug 10 20:43:46 2011\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Aug 20 23:09:36 2011\r
Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
*/\r
\r
reg r_hld_vram_start;\r
wire [7:0] w_wrdata1;\r
wire [7:0] w_wrdata2;\r
+ wire [7:0] w_wradrs1;\r
+ wire [7:0] w_wradrs2;\r
wire fs_fifo1_write;\r
wire fs_fifo2_write;\r
wire fs_init;\r
wire fs_fifo1_charge;\r
wire fs_fifo2_charge;\r
wire fs_vram_cnt_inc;\r
- wire [13:0] _net_55;\r
- wire [13:0] _net_58;\r
- wire [13:0] _net_61;\r
- wire [13:0] _net_64;\r
- wire [13:0] _net_67;\r
+ reg [7:0] r_wradrs1;\r
+ reg [7:0] r_wradrs2;\r
+ wire [13:0] _net_57;\r
+ wire [13:0] _net_60;\r
+ wire [13:0] _net_63;\r
+ wire [13:0] _net_66;\r
+ wire [13:0] _net_69;\r
wire _u_VGA_i_clk50M;\r
wire _u_VGA_m_clock;\r
wire _u_VGA_p_reset;\r
wire [3:0] _u_VGA_o_vga_b;\r
wire [7:0] _u_VGA_i_wrdata1;\r
wire [7:0] _u_VGA_i_wrdata2;\r
+ wire [7:0] _u_VGA_i_wradrs1;\r
+ wire [7:0] _u_VGA_i_wradrs2;\r
wire _u_VGA_fi_fifo1_write;\r
wire _u_VGA_fi_fifo2_write;\r
- wire _u_VGA_fi_fifo1_reset;\r
- wire _u_VGA_fi_fifo2_reset;\r
wire _u_VGA_outled;\r
wire [9:0] _u_VGA_o_vcnt;\r
wire [13:0] _u_EXP_i_Radrs;\r
wire _u_EXP_fi_Wr_req;\r
wire _u_EXP_p_reset;\r
wire _u_EXP_m_clock;\r
- wire _net_68;\r
- wire _net_69;\r
wire _net_70;\r
wire _net_71;\r
wire _net_72;\r
wire _net_73;\r
wire _net_74;\r
- reg _reg_75;\r
- reg _reg_76;\r
+ wire _net_75;\r
+ wire _net_76;\r
reg _reg_77;\r
reg _reg_78;\r
reg _reg_79;\r
reg _reg_88;\r
reg _reg_89;\r
reg _reg_90;\r
- wire _net_91;\r
- wire _reg_77_goto;\r
- wire _net_92;\r
- wire _reg_80_goin;\r
+ reg _reg_91;\r
+ reg _reg_92;\r
wire _net_93;\r
- wire _net_94;\r
wire _reg_80_goto;\r
+ wire _net_94;\r
+ wire _reg_83_goin;\r
wire _net_95;\r
- wire _reg_76_goin;\r
wire _net_96;\r
+ wire _reg_83_goto;\r
wire _net_97;\r
+ wire _reg_79_goin;\r
wire _net_98;\r
wire _net_99;\r
- wire _reg_82_goto;\r
wire _net_100;\r
- wire _reg_85_goin;\r
wire _net_101;\r
+ wire _reg_86_goto;\r
wire _net_102;\r
- wire _reg_85_goto;\r
+ wire _reg_89_goin;\r
wire _net_103;\r
- wire _reg_81_goin;\r
wire _net_104;\r
+ wire _reg_89_goto;\r
wire _net_105;\r
+ wire _reg_85_goin;\r
wire _net_106;\r
wire _net_107;\r
- wire _reg_87_goto;\r
wire _net_108;\r
- wire _reg_86_goin;\r
wire _net_109;\r
+ wire _reg_91_goto;\r
wire _net_110;\r
+ wire _reg_90_goin;\r
wire _net_111;\r
wire _net_112;\r
wire _net_113;\r
wire _net_114;\r
- wire _reg_87_goin;\r
wire _net_115;\r
wire _net_116;\r
+ wire _reg_91_goin;\r
wire _net_117;\r
wire _net_118;\r
wire _net_119;\r
wire _net_132;\r
wire _net_133;\r
wire _net_134;\r
- reg _reg_135;\r
- reg _reg_136;\r
+ wire _net_135;\r
+ wire _net_136;\r
reg _reg_137;\r
reg _reg_138;\r
reg _reg_139;\r
reg _reg_140;\r
- wire _net_141;\r
- wire _reg_135_goto;\r
- wire _net_142;\r
- wire _reg_138_goin;\r
+ reg _reg_141;\r
+ reg _reg_142;\r
wire _net_143;\r
- wire _net_144;\r
wire _reg_138_goto;\r
+ wire _net_144;\r
+ wire _reg_141_goin;\r
wire _net_145;\r
wire _net_146;\r
+ wire _reg_141_goto;\r
wire _net_147;\r
+ wire _reg_137_goin;\r
wire _net_148;\r
wire _net_149;\r
wire _net_150;\r
wire _net_151;\r
wire _net_152;\r
wire _net_153;\r
- reg _reg_154;\r
- reg _reg_155;\r
- reg _reg_156;\r
+ wire _net_154;\r
+ wire _net_155;\r
+ wire _net_156;\r
reg _reg_157;\r
reg _reg_158;\r
reg _reg_159;\r
reg _reg_160;\r
- wire _net_161;\r
- wire _reg_155_goto;\r
- wire _net_162;\r
- wire _reg_158_goin;\r
- wire _net_163;\r
+ reg _reg_161;\r
+ reg _reg_162;\r
+ reg _reg_163;\r
wire _net_164;\r
- wire _reg_158_goto;\r
+ wire _reg_159_goto;\r
wire _net_165;\r
- wire _reg_154_goin;\r
+ wire _reg_162_goin;\r
wire _net_166;\r
wire _net_167;\r
+ wire _reg_162_goto;\r
wire _net_168;\r
+ wire _reg_158_goin;\r
wire _net_169;\r
wire _net_170;\r
wire _net_171;\r
wire _net_176;\r
wire _net_177;\r
wire _net_178;\r
+ wire _net_179;\r
+ wire _net_180;\r
+ wire _net_181;\r
exp_ctrl u_EXP (.p_reset(p_reset), .m_clock(m_clock), .fi_Wr_req(_u_EXP_fi_Wr_req), .i_Wadrs(_u_EXP_i_Wadrs), .i_Wdata(_u_EXP_i_Wdata), .fo_Rd_ack(_u_EXP_fo_Rd_ack), .fi_Rd_req(_u_EXP_fi_Rd_req), .o_Rdata(_u_EXP_o_Rdata), .i_Radrs(_u_EXP_i_Radrs));\r
-vga_gen u_VGA (.o_vcnt(_u_VGA_o_vcnt), .outled(_u_VGA_outled), .fi_fifo2_reset(_u_VGA_fi_fifo2_reset), .fi_fifo1_reset(_u_VGA_fi_fifo1_reset), .fi_fifo2_write(_u_VGA_fi_fifo2_write), .fi_fifo1_write(_u_VGA_fi_fifo1_write), .i_wrdata2(_u_VGA_i_wrdata2), .i_wrdata1(_u_VGA_i_wrdata1), .o_vga_b(_u_VGA_o_vga_b), .o_vga_g(_u_VGA_o_vga_g), .o_vga_r(_u_VGA_o_vga_r), .o_hsync(_u_VGA_o_hsync), .o_vsync(_u_VGA_o_vsync), .p_reset(_u_VGA_p_reset), .m_clock(_u_VGA_m_clock), .i_clk50M(_u_VGA_i_clk50M));\r
+vga_gen u_VGA (.o_vcnt(_u_VGA_o_vcnt), .outled(_u_VGA_outled), .fi_fifo2_write(_u_VGA_fi_fifo2_write), .fi_fifo1_write(_u_VGA_fi_fifo1_write), .i_wradrs2(_u_VGA_i_wradrs2), .i_wradrs1(_u_VGA_i_wradrs1), .i_wrdata2(_u_VGA_i_wrdata2), .i_wrdata1(_u_VGA_i_wrdata1), .o_vga_b(_u_VGA_o_vga_b), .o_vga_g(_u_VGA_o_vga_g), .o_vga_r(_u_VGA_o_vga_r), .o_hsync(_u_VGA_o_hsync), .o_vsync(_u_VGA_o_vsync), .p_reset(_u_VGA_p_reset), .m_clock(_u_VGA_m_clock), .i_clk50M(_u_VGA_i_clk50M));\r
\r
- assign w_wrdata1 = ((_reg_136|_reg_83)?r_vram_rddata[7:0]:8'b0)|\r
- ((_reg_135|_reg_82)?r_vram_rddata[15:8]:8'b0);\r
- assign w_wrdata2 = ((_reg_156|_reg_78)?r_vram_rddata[7:0]:8'b0)|\r
- ((_reg_155|_reg_77)?r_vram_rddata[15:8]:8'b0);\r
- assign fs_fifo1_write = _reg_136|_reg_135|_reg_83|_reg_82;\r
- assign fs_fifo2_write = _reg_156|_reg_155|_reg_78|_reg_77;\r
- assign fs_init = _net_68;\r
+ assign w_wrdata1 = ((_reg_139|_reg_87)?r_vram_rddata[7:0]:8'b0)|\r
+ ((_reg_138|_reg_86)?r_vram_rddata[15:8]:8'b0);\r
+ assign w_wrdata2 = ((_reg_160|_reg_81)?r_vram_rddata[7:0]:8'b0)|\r
+ ((_reg_159|_reg_80)?r_vram_rddata[15:8]:8'b0);\r
+ assign w_wradrs1 = r_wradrs1;\r
+ assign w_wradrs2 = r_wradrs2;\r
+ assign fs_fifo1_write = _reg_139|_reg_138|_reg_87|_reg_86;\r
+ assign fs_fifo2_write = _reg_160|_reg_159|_reg_81|_reg_80;\r
+ assign fs_init = _net_70;\r
assign fs_fifo1_charge = _net_72;\r
- assign fs_fifo2_charge = _net_70;\r
- assign fs_vram_cnt_inc = _reg_154;\r
- assign _net_55 = (r_init_cnt)+(14'b00000000000001);\r
- assign _net_58 = (r_init_cnt)+(14'b00000000000001);\r
- assign _net_61 = (r_init_cnt)+(14'b00000000000001);\r
- assign _net_64 = (r_init_cnt)+(14'b00000000000001);\r
- assign _net_67 = (r_init_cnt)+(14'b00000000000001);\r
+ assign fs_fifo2_charge = _net_74;\r
+ assign fs_vram_cnt_inc = _reg_157;\r
+ assign _net_57 = (r_init_cnt)+(14'b00000000000001);\r
+ assign _net_60 = (r_init_cnt)+(14'b00000000000001);\r
+ assign _net_63 = (r_init_cnt)+(14'b00000000000001);\r
+ assign _net_66 = (r_init_cnt)+(14'b00000000000001);\r
+ assign _net_69 = (r_init_cnt)+(14'b00000000000001);\r
assign _u_VGA_i_clk50M = m_clock;\r
assign _u_VGA_m_clock = r_cnt;\r
assign _u_VGA_p_reset = r_reset;\r
assign _u_VGA_i_wrdata1 = w_wrdata1;\r
assign _u_VGA_i_wrdata2 = w_wrdata2;\r
+ assign _u_VGA_i_wradrs1 = w_wradrs1;\r
+ assign _u_VGA_i_wradrs2 = w_wradrs2;\r
assign _u_VGA_fi_fifo1_write = fs_fifo1_write;\r
assign _u_VGA_fi_fifo2_write = fs_fifo2_write;\r
- assign _u_VGA_fi_fifo1_reset = _net_148|_net_119;\r
- assign _u_VGA_fi_fifo2_reset = _net_169|_reg_89;\r
assign _u_EXP_i_Radrs = r_init_cnt;\r
- assign _u_EXP_fi_Rd_req = _net_167|_net_146|_net_105|_net_97;\r
+ assign _u_EXP_fi_Rd_req = _net_170|_net_149|_net_107|_net_99;\r
assign _u_EXP_i_Wdata = 8'b00001111;\r
assign _u_EXP_i_Wadrs = r_init_cnt;\r
- assign _u_EXP_fi_Wr_req = _net_116;\r
- assign _net_68 = (trigger)==(3'b011);\r
- assign _net_69 = (~r_hld_vram_start)&(_u_VGA_o_vcnt[0]);\r
- assign _net_70 = r_reset&_net_69;\r
- assign _net_71 = r_hld_vram_start&(~(_u_VGA_o_vcnt[0]));\r
+ assign _u_EXP_fi_Wr_req = _net_118;\r
+ assign _net_70 = (trigger)==(3'b011);\r
+ assign _net_71 = (~r_hld_vram_start)&(_u_VGA_o_vcnt[0]);\r
assign _net_72 = r_reset&_net_71;\r
- assign _net_73 = (r_sec_cnt)==(26'b10111110101111000010000000);\r
- assign _net_74 = ~_net_73;\r
- assign _net_91 = (_net_61) < (14'b00000000101000);\r
- assign _reg_77_goto = _net_92;\r
- assign _net_92 = _reg_77&_net_91;\r
- assign _reg_80_goin = _net_93;\r
- assign _net_93 = _reg_77&_net_91;\r
- assign _net_94 = ~((r_init_cnt) < (14'b00000000101000));\r
- assign _reg_80_goto = _net_95;\r
- assign _net_95 = _reg_80&_net_94;\r
- assign _reg_76_goin = _net_96;\r
- assign _net_96 = _reg_80&_net_94;\r
- assign _net_97 = _reg_80&(~_net_94);\r
- assign _net_98 = _reg_80&(~_net_94);\r
- assign _net_99 = (_net_58) < (14'b00000000101000);\r
- assign _reg_82_goto = _net_100;\r
- assign _net_100 = _reg_82&_net_99;\r
- assign _reg_85_goin = _net_101;\r
- assign _net_101 = _reg_82&_net_99;\r
- assign _net_102 = ~((r_init_cnt) < (14'b00000000101000));\r
- assign _reg_85_goto = _net_103;\r
- assign _net_103 = _reg_85&_net_102;\r
- assign _reg_81_goin = _net_104;\r
- assign _net_104 = _reg_85&_net_102;\r
- assign _net_105 = _reg_85&(~_net_102);\r
- assign _net_106 = _reg_85&(~_net_102);\r
- assign _net_107 = ~((r_init_cnt) < (14'b10010110000000));\r
- assign _reg_87_goto = _net_114|_net_108;\r
- assign _net_108 = _reg_87&_net_107;\r
- assign _reg_86_goin = _net_109;\r
- assign _net_109 = _reg_87&_net_107;\r
- assign _net_110 = _reg_87&(~_net_107);\r
- assign _net_111 = _reg_87&(~_net_107);\r
- assign _net_112 = (_net_55) < (14'b10010110000000);\r
- assign _net_113 = _reg_87&(~_net_107);\r
- assign _net_114 = (_reg_87&(~_net_107))&_net_112;\r
- assign _reg_87_goin = _net_115;\r
- assign _net_115 = (_reg_87&(~_net_107))&_net_112;\r
- assign _net_116 = _reg_87&(~_net_107);\r
- assign _net_117 = _reg_87&(~_net_107);\r
- assign _net_118 = _reg_87&(~_net_107);\r
- assign _net_119 = fs_init|_reg_90;\r
- assign _net_120 = fs_init|_reg_89|_reg_90;\r
- assign _net_121 = fs_init|_reg_88|_reg_89;\r
- assign _net_122 = _reg_87_goin|_reg_87|_reg_88;\r
- assign _net_123 = _reg_86_goin|_reg_86|_reg_87;\r
- assign _net_124 = _reg_85_goin|_reg_85|_reg_86;\r
- assign _net_125 = _reg_85_goin|_reg_84|_reg_85;\r
- assign _net_126 = _reg_85_goin|_reg_83|_reg_84;\r
- assign _net_127 = _reg_85_goin|_reg_82|_reg_83;\r
- assign _net_128 = _reg_81_goin|_reg_81|_reg_82;\r
- assign _net_129 = _reg_80_goin|_reg_80|_reg_81;\r
- assign _net_130 = _reg_80_goin|_reg_79|_reg_80;\r
- assign _net_131 = _reg_80_goin|_reg_78|_reg_79;\r
- assign _net_132 = _reg_80_goin|_reg_77|_reg_78;\r
- assign _net_133 = _reg_76_goin|_reg_76|_reg_77;\r
- assign _net_134 = _reg_76_goin|_reg_75|_reg_76;\r
- assign _net_141 = (_net_64) < (14'b00000000101000);\r
- assign _reg_135_goto = _net_142;\r
- assign _net_142 = _reg_135&_net_141;\r
- assign _reg_138_goin = _net_143;\r
- assign _net_143 = _reg_135&_net_141;\r
- assign _net_144 = ~((r_init_cnt) < (14'b00000000101000));\r
- assign _reg_138_goto = _net_145;\r
- assign _net_145 = _reg_138&_net_144;\r
- assign _net_146 = _reg_138&(~_net_144);\r
- assign _net_147 = _reg_138&(~_net_144);\r
- assign _net_148 = fs_fifo1_charge|_reg_140;\r
- assign _net_149 = fs_fifo1_charge|_reg_139|_reg_140;\r
- assign _net_150 = _reg_138_goin|_reg_138|_reg_139;\r
- assign _net_151 = _reg_138_goin|_reg_137|_reg_138;\r
- assign _net_152 = _reg_138_goin|_reg_136|_reg_137;\r
- assign _net_153 = _reg_138_goin|_reg_135|_reg_136;\r
- assign _net_161 = (_net_67) < (14'b00000000101000);\r
- assign _reg_155_goto = _net_162;\r
- assign _net_162 = _reg_155&_net_161;\r
- assign _reg_158_goin = _net_163;\r
- assign _net_163 = _reg_155&_net_161;\r
- assign _net_164 = ~((r_init_cnt) < (14'b00000000101000));\r
- assign _reg_158_goto = _net_165;\r
- assign _net_165 = _reg_158&_net_164;\r
- assign _reg_154_goin = _net_166;\r
- assign _net_166 = _reg_158&_net_164;\r
- assign _net_167 = _reg_158&(~_net_164);\r
- assign _net_168 = _reg_158&(~_net_164);\r
- assign _net_169 = fs_fifo2_charge|_reg_160;\r
- assign _net_170 = fs_fifo2_charge|_reg_159|_reg_160;\r
- assign _net_171 = _reg_158_goin|_reg_158|_reg_159;\r
- assign _net_172 = _reg_158_goin|_reg_157|_reg_158;\r
- assign _net_173 = _reg_158_goin|_reg_156|_reg_157;\r
- assign _net_174 = _reg_158_goin|_reg_155|_reg_156;\r
- assign _net_175 = _reg_154_goin|_reg_154|_reg_155;\r
- assign _net_176 = (r_vram_start_adrs)==(14'b10010101011000);\r
- assign _net_177 = fs_vram_cnt_inc&_net_176;\r
- assign _net_178 = fs_vram_cnt_inc&(~_net_176);\r
+ assign _net_73 = r_hld_vram_start&(~(_u_VGA_o_vcnt[0]));\r
+ assign _net_74 = r_reset&_net_73;\r
+ assign _net_75 = (r_sec_cnt)==(26'b10111110101111000010000000);\r
+ assign _net_76 = ~_net_75;\r
+ assign _net_93 = (_net_63) < (14'b00000000101000);\r
+ assign _reg_80_goto = _net_94;\r
+ assign _net_94 = _reg_80&_net_93;\r
+ assign _reg_83_goin = _net_95;\r
+ assign _net_95 = _reg_80&_net_93;\r
+ assign _net_96 = ~((r_init_cnt) < (14'b00000000101000));\r
+ assign _reg_83_goto = _net_97;\r
+ assign _net_97 = _reg_83&_net_96;\r
+ assign _reg_79_goin = _net_98;\r
+ assign _net_98 = _reg_83&_net_96;\r
+ assign _net_99 = _reg_83&(~_net_96);\r
+ assign _net_100 = _reg_83&(~_net_96);\r
+ assign _net_101 = (_net_60) < (14'b00000000101000);\r
+ assign _reg_86_goto = _net_102;\r
+ assign _net_102 = _reg_86&_net_101;\r
+ assign _reg_89_goin = _net_103;\r
+ assign _net_103 = _reg_86&_net_101;\r
+ assign _net_104 = ~((r_init_cnt) < (14'b00000000101000));\r
+ assign _reg_89_goto = _net_105;\r
+ assign _net_105 = _reg_89&_net_104;\r
+ assign _reg_85_goin = _net_106;\r
+ assign _net_106 = _reg_89&_net_104;\r
+ assign _net_107 = _reg_89&(~_net_104);\r
+ assign _net_108 = _reg_89&(~_net_104);\r
+ assign _net_109 = ~((r_init_cnt) < (14'b10010110000000));\r
+ assign _reg_91_goto = _net_116|_net_110;\r
+ assign _net_110 = _reg_91&_net_109;\r
+ assign _reg_90_goin = _net_111;\r
+ assign _net_111 = _reg_91&_net_109;\r
+ assign _net_112 = _reg_91&(~_net_109);\r
+ assign _net_113 = _reg_91&(~_net_109);\r
+ assign _net_114 = (_net_57) < (14'b10010110000000);\r
+ assign _net_115 = _reg_91&(~_net_109);\r
+ assign _net_116 = (_reg_91&(~_net_109))&_net_114;\r
+ assign _reg_91_goin = _net_117;\r
+ assign _net_117 = (_reg_91&(~_net_109))&_net_114;\r
+ assign _net_118 = _reg_91&(~_net_109);\r
+ assign _net_119 = _reg_91&(~_net_109);\r
+ assign _net_120 = _reg_91&(~_net_109);\r
+ assign _net_121 = fs_init|_reg_92;\r
+ assign _net_122 = (_reg_91_goin|fs_init)|_reg_91|_reg_92;\r
+ assign _net_123 = _reg_90_goin|_reg_90|_reg_91;\r
+ assign _net_124 = _reg_89_goin|_reg_89|_reg_90;\r
+ assign _net_125 = _reg_89_goin|_reg_88|_reg_89;\r
+ assign _net_126 = _reg_89_goin|_reg_87|_reg_88;\r
+ assign _net_127 = _reg_89_goin|_reg_86|_reg_87;\r
+ assign _net_128 = _reg_85_goin|_reg_85|_reg_86;\r
+ assign _net_129 = _reg_85_goin|_reg_84|_reg_85;\r
+ assign _net_130 = _reg_83_goin|_reg_83|_reg_84;\r
+ assign _net_131 = _reg_83_goin|_reg_82|_reg_83;\r
+ assign _net_132 = _reg_83_goin|_reg_81|_reg_82;\r
+ assign _net_133 = _reg_83_goin|_reg_80|_reg_81;\r
+ assign _net_134 = _reg_79_goin|_reg_79|_reg_80;\r
+ assign _net_135 = _reg_79_goin|_reg_78|_reg_79;\r
+ assign _net_136 = _reg_79_goin|_reg_77|_reg_78;\r
+ assign _net_143 = (_net_66) < (14'b00000000101000);\r
+ assign _reg_138_goto = _net_144;\r
+ assign _net_144 = _reg_138&_net_143;\r
+ assign _reg_141_goin = _net_145;\r
+ assign _net_145 = _reg_138&_net_143;\r
+ assign _net_146 = ~((r_init_cnt) < (14'b00000000101000));\r
+ assign _reg_141_goto = _net_147;\r
+ assign _net_147 = _reg_141&_net_146;\r
+ assign _reg_137_goin = _net_148;\r
+ assign _net_148 = _reg_141&_net_146;\r
+ assign _net_149 = _reg_141&(~_net_146);\r
+ assign _net_150 = _reg_141&(~_net_146);\r
+ assign _net_151 = fs_fifo1_charge|_reg_142;\r
+ assign _net_152 = (_reg_141_goin|fs_fifo1_charge)|_reg_141|_reg_142;\r
+ assign _net_153 = (_reg_141_goin|fs_fifo1_charge)|_reg_140|_reg_141;\r
+ assign _net_154 = (_reg_141_goin|fs_fifo1_charge)|_reg_139|_reg_140;\r
+ assign _net_155 = (_reg_141_goin|fs_fifo1_charge)|_reg_138|_reg_139;\r
+ assign _net_156 = _reg_137_goin|_reg_137|_reg_138;\r
+ assign _net_164 = (_net_69) < (14'b00000000101000);\r
+ assign _reg_159_goto = _net_165;\r
+ assign _net_165 = _reg_159&_net_164;\r
+ assign _reg_162_goin = _net_166;\r
+ assign _net_166 = _reg_159&_net_164;\r
+ assign _net_167 = ~((r_init_cnt) < (14'b00000000101000));\r
+ assign _reg_162_goto = _net_168;\r
+ assign _net_168 = _reg_162&_net_167;\r
+ assign _reg_158_goin = _net_169;\r
+ assign _net_169 = _reg_162&_net_167;\r
+ assign _net_170 = _reg_162&(~_net_167);\r
+ assign _net_171 = _reg_162&(~_net_167);\r
+ assign _net_172 = fs_fifo2_charge|_reg_163;\r
+ assign _net_173 = (_reg_162_goin|fs_fifo2_charge)|_reg_162|_reg_163;\r
+ assign _net_174 = (_reg_162_goin|fs_fifo2_charge)|_reg_161|_reg_162;\r
+ assign _net_175 = (_reg_162_goin|fs_fifo2_charge)|_reg_160|_reg_161;\r
+ assign _net_176 = (_reg_162_goin|fs_fifo2_charge)|_reg_159|_reg_160;\r
+ assign _net_177 = _reg_158_goin|_reg_158|_reg_159;\r
+ assign _net_178 = _reg_158_goin|_reg_157|_reg_158;\r
+ assign _net_179 = (r_vram_start_adrs)==(14'b10010101011000);\r
+ assign _net_180 = fs_vram_cnt_inc&_net_179;\r
+ assign _net_181 = fs_vram_cnt_inc&(~_net_179);\r
assign o_vsync = _u_VGA_o_vsync;\r
assign o_hsync = _u_VGA_o_hsync;\r
assign o_vga_r = _u_VGA_o_vga_r;\r
begin\r
if (~p_reset)\r
r_reset <= 1'b0;\r
-else if ((_reg_75)) \r
+else if ((_reg_77)) \r
r_reset <= 1'b1;\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
r_sec_cnt <= 26'b00000000000000000000000000;\r
-else if ((_net_74)|(_net_73)) \r
- r_sec_cnt <= ((_net_74) ?(r_sec_cnt)+(26'b00000000000000000000000001):26'b0)|\r
- ((_net_73) ?26'b00000000000000000000000000:26'b0);\r
+else if ((_net_76)|(_net_75)) \r
+ r_sec_cnt <= ((_net_76) ?(r_sec_cnt)+(26'b00000000000000000000000001):26'b0)|\r
+ ((_net_75) ?26'b00000000000000000000000000:26'b0);\r
\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
r_LED <= 1'b0;\r
-else if ((_net_73)) \r
+else if ((_net_75)) \r
r_LED <= ~r_LED;\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
r_init_cnt <= 14'b00000000000000;\r
-else if ((_reg_155)|(_reg_135)|(_net_110)|(_reg_82)|(_reg_159|_reg_139|_reg_88|_reg_86|_reg_81)|(_reg_77)) \r
- r_init_cnt <= ((_reg_155) ?_net_67:14'b0)|\r
- ((_reg_135) ?_net_64:14'b0)|\r
- ((_net_110) ?_net_55:14'b0)|\r
- ((_reg_82) ?_net_58:14'b0)|\r
- ((_reg_159|_reg_139|_reg_88|_reg_86|_reg_81) ?14'b00000000000000:14'b0)|\r
- ((_reg_77) ?_net_61:14'b0);\r
+else if ((_reg_159)|(_reg_138)|(_net_112)|(_reg_86)|(_net_172|_net_151|_net_121|_reg_90|_reg_84)|(_reg_80)) \r
+ r_init_cnt <= ((_reg_159) ?_net_69:14'b0)|\r
+ ((_reg_138) ?_net_66:14'b0)|\r
+ ((_net_112) ?_net_57:14'b0)|\r
+ ((_reg_86) ?_net_60:14'b0)|\r
+ ((_net_172|_net_151|_net_121|_reg_90|_reg_84) ?14'b00000000000000:14'b0)|\r
+ ((_reg_80) ?_net_63:14'b0);\r
\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
r_vram_rddata <= 16'b0000000000000000;\r
-else if ((_reg_157|_reg_137|_reg_84|_reg_79)) \r
+else if ((_reg_161|_reg_140|_reg_88|_reg_82)) \r
r_vram_rddata <= _u_EXP_o_Rdata;\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
r_vram_start_adrs <= 14'b00000000000000;\r
-else if ((_net_177)|(_net_178|_reg_76)) \r
- r_vram_start_adrs <= ((_net_177) ?14'b00000000000000:14'b0)|\r
- ((_net_178|_reg_76) ?(r_vram_start_adrs)+(14'b00000000101000):14'b0);\r
+else if ((_net_180)|(_net_181|_reg_78)) \r
+ r_vram_start_adrs <= ((_net_180) ?14'b00000000000000:14'b0)|\r
+ ((_net_181|_reg_78) ?(r_vram_start_adrs)+(14'b00000000101000):14'b0);\r
\r
end\r
always @(posedge m_clock or negedge p_reset)\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
- _reg_75 <= 1'b0;\r
-else if ((_net_134)) \r
- _reg_75 <= _reg_76;\r
+ r_wradrs1 <= 8'b00000000;\r
+else if ((_reg_139|_reg_138|_reg_87|_reg_86)|(_reg_137|_reg_85)) \r
+ r_wradrs1 <= ((_reg_139|_reg_138|_reg_87|_reg_86) ?(r_wradrs1)+(8'b00000001):8'b0)|\r
+ ((_reg_137|_reg_85) ?8'b00000000:8'b0);\r
+\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
- _reg_76 <= 1'b0;\r
-else if ((_net_133)) \r
- _reg_76 <= _reg_76_goin|(_reg_77&(~_reg_77_goto));\r
+ r_wradrs2 <= 8'b00000000;\r
+else if ((_reg_160|_reg_159|_reg_81|_reg_80)|(_reg_158|_reg_79)) \r
+ r_wradrs2 <= ((_reg_160|_reg_159|_reg_81|_reg_80) ?(r_wradrs2)+(8'b00000001):8'b0)|\r
+ ((_reg_158|_reg_79) ?8'b00000000:8'b0);\r
+\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
_reg_77 <= 1'b0;\r
-else if ((_net_132)) \r
+else if ((_net_136)) \r
_reg_77 <= _reg_78;\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
_reg_78 <= 1'b0;\r
-else if ((_net_131)) \r
+else if ((_net_135)) \r
_reg_78 <= _reg_79;\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
_reg_79 <= 1'b0;\r
-else if ((_net_130)) \r
- _reg_79 <= _reg_80&(~_reg_80_goto);\r
+else if ((_net_134)) \r
+ _reg_79 <= _reg_79_goin|(_reg_80&(~_reg_80_goto));\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
_reg_80 <= 1'b0;\r
-else if ((_net_129)) \r
- _reg_80 <= _reg_80_goin|_reg_81;\r
+else if ((_net_133)) \r
+ _reg_80 <= _reg_81;\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
_reg_81 <= 1'b0;\r
-else if ((_net_128)) \r
- _reg_81 <= _reg_81_goin|(_reg_82&(~_reg_82_goto));\r
+else if ((_net_132)) \r
+ _reg_81 <= _reg_82;\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
_reg_82 <= 1'b0;\r
-else if ((_net_127)) \r
- _reg_82 <= _reg_83;\r
+else if ((_net_131)) \r
+ _reg_82 <= _reg_83&(~_reg_83_goto);\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
_reg_83 <= 1'b0;\r
-else if ((_net_126)) \r
- _reg_83 <= _reg_84;\r
+else if ((_net_130)) \r
+ _reg_83 <= _reg_83_goin|_reg_84;\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
_reg_84 <= 1'b0;\r
-else if ((_net_125)) \r
- _reg_84 <= _reg_85&(~_reg_85_goto);\r
+else if ((_net_129)) \r
+ _reg_84 <= _reg_85;\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
_reg_85 <= 1'b0;\r
-else if ((_net_124)) \r
- _reg_85 <= _reg_85_goin|_reg_86;\r
+else if ((_net_128)) \r
+ _reg_85 <= _reg_85_goin|(_reg_86&(~_reg_86_goto));\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
_reg_86 <= 1'b0;\r
-else if ((_net_123)) \r
- _reg_86 <= _reg_86_goin|(_reg_87&(~_reg_87_goto));\r
+else if ((_net_127)) \r
+ _reg_86 <= _reg_87;\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
_reg_87 <= 1'b0;\r
-else if ((_net_122)) \r
- _reg_87 <= _reg_87_goin|_reg_88;\r
+else if ((_net_126)) \r
+ _reg_87 <= _reg_88;\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
_reg_88 <= 1'b0;\r
-else if ((_net_121)) \r
- _reg_88 <= _reg_89;\r
+else if ((_net_125)) \r
+ _reg_88 <= _reg_89&(~_reg_89_goto);\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
_reg_89 <= 1'b0;\r
-else if ((_net_120)) \r
- _reg_89 <= _reg_90|fs_init;\r
+else if ((_net_124)) \r
+ _reg_89 <= _reg_89_goin|_reg_90;\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
_reg_90 <= 1'b0;\r
-else if ((_reg_90)) \r
- _reg_90 <= 1'b0;\r
+else if ((_net_123)) \r
+ _reg_90 <= _reg_90_goin|(_reg_91&(~_reg_91_goto));\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
- _reg_135 <= 1'b0;\r
-else if ((_net_153)) \r
- _reg_135 <= _reg_136;\r
+ _reg_91 <= 1'b0;\r
+else if ((_net_122)) \r
+ _reg_91 <= (_reg_91_goin|_reg_92)|fs_init;\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
- _reg_136 <= 1'b0;\r
-else if ((_net_152)) \r
- _reg_136 <= _reg_137;\r
+ _reg_92 <= 1'b0;\r
+else if ((_reg_92)) \r
+ _reg_92 <= 1'b0;\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
_reg_137 <= 1'b0;\r
-else if ((_net_151)) \r
- _reg_137 <= _reg_138&(~_reg_138_goto);\r
+else if ((_net_156)) \r
+ _reg_137 <= _reg_137_goin|(_reg_138&(~_reg_138_goto));\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
_reg_138 <= 1'b0;\r
-else if ((_net_150)) \r
- _reg_138 <= _reg_138_goin|_reg_139;\r
+else if ((_net_155)) \r
+ _reg_138 <= _reg_139;\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
_reg_139 <= 1'b0;\r
-else if ((_net_149)) \r
- _reg_139 <= _reg_140|fs_fifo1_charge;\r
+else if ((_net_154)) \r
+ _reg_139 <= _reg_140;\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
_reg_140 <= 1'b0;\r
-else if ((_reg_140)) \r
- _reg_140 <= 1'b0;\r
-end\r
-always @(posedge m_clock or negedge p_reset)\r
- begin\r
-if (~p_reset)\r
- _reg_154 <= 1'b0;\r
-else if ((_net_175)) \r
- _reg_154 <= _reg_154_goin|(_reg_155&(~_reg_155_goto));\r
+else if ((_net_153)) \r
+ _reg_140 <= _reg_141&(~_reg_141_goto);\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
- _reg_155 <= 1'b0;\r
-else if ((_net_174)) \r
- _reg_155 <= _reg_156;\r
+ _reg_141 <= 1'b0;\r
+else if ((_net_152)) \r
+ _reg_141 <= (_reg_141_goin|_reg_142)|fs_fifo1_charge;\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
- _reg_156 <= 1'b0;\r
-else if ((_net_173)) \r
- _reg_156 <= _reg_157;\r
+ _reg_142 <= 1'b0;\r
+else if ((_reg_142)) \r
+ _reg_142 <= 1'b0;\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
_reg_157 <= 1'b0;\r
-else if ((_net_172)) \r
- _reg_157 <= _reg_158&(~_reg_158_goto);\r
+else if ((_net_178)) \r
+ _reg_157 <= _reg_158;\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
_reg_158 <= 1'b0;\r
-else if ((_net_171)) \r
- _reg_158 <= _reg_158_goin|_reg_159;\r
+else if ((_net_177)) \r
+ _reg_158 <= _reg_158_goin|(_reg_159&(~_reg_159_goto));\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
_reg_159 <= 1'b0;\r
-else if ((_net_170)) \r
- _reg_159 <= _reg_160|fs_fifo2_charge;\r
+else if ((_net_176)) \r
+ _reg_159 <= _reg_160;\r
end\r
always @(posedge m_clock or negedge p_reset)\r
begin\r
if (~p_reset)\r
_reg_160 <= 1'b0;\r
-else if ((_reg_160)) \r
- _reg_160 <= 1'b0;\r
+else if ((_net_175)) \r
+ _reg_160 <= _reg_161;\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ _reg_161 <= 1'b0;\r
+else if ((_net_174)) \r
+ _reg_161 <= _reg_162&(~_reg_162_goto);\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ _reg_162 <= 1'b0;\r
+else if ((_net_173)) \r
+ _reg_162 <= (_reg_162_goin|_reg_163)|fs_fifo2_charge;\r
+end\r
+always @(posedge m_clock or negedge p_reset)\r
+ begin\r
+if (~p_reset)\r
+ _reg_163 <= 1'b0;\r
+else if ((_reg_163)) \r
+ _reg_163 <= 1'b0;\r
end\r
endmodule\r
/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Wed Aug 10 20:43:49 2011\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Aug 20 23:09:39 2011\r
Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
*/\r
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