VRAM FIFO VGAgen VGAtop連結完了

[oca1/test.git] / VGADisplay / Verilog / vram_ctrl.v

diff --git a/VGADisplay/Verilog/vram_ctrl.v b/VGADisplay/Verilog/vram_ctrl.v
index b2a6a66..87dd8aa 100644 (file)
--- a/VGADisplay/Verilog/vram_ctrl.v
+++ b/VGADisplay/Verilog/vram_ctrl.v
@@ -1,5 +1,5 @@
 /*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Wed Jul 20 21:25:23 2011\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Fri Aug 12 17:25:22 2011\r
  Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER:\r
 */\r
 \r
@@ -13,11 +13,11 @@ module vram_ctrl ( p_reset , m_clock , i_Wdata , i_Wadrs , i_Radrs , o_Rdata , f
   input fi_Rd_req;\r
   output fo_Rd_ack;\r
   reg [13:0] r_Radrs_hld;\r
-  wire _u_VRAM_clk;\r
-  wire [7:0] _u_VRAM_d;\r
-  wire [13:0] _u_VRAM_ra;\r
-  wire [13:0] _u_VRAM_wa;\r
-  wire _u_VRAM_we;\r
+  wire _u_VRAM_clock;\r
+  wire [7:0] _u_VRAM_data;\r
+  wire [13:0] _u_VRAM_rdaddress;\r
+  wire [13:0] _u_VRAM_wraddress;\r
+  wire _u_VRAM_wren;\r
   wire [7:0] _u_VRAM_q;\r
   wire _u_VRAM_p_reset;\r
   wire _u_VRAM_m_clock;\r
@@ -26,40 +26,41 @@ module vram_ctrl ( p_reset , m_clock , i_Wdata , i_Wadrs , i_Radrs , o_Rdata , f
   reg _reg_2;\r
   wire _net_3;\r
   wire _net_4;\r
-vram u_VRAM (.p_reset(p_reset), .m_clock(m_clock), .q(_u_VRAM_q), .we(_u_VRAM_we), .wa(_u_VRAM_wa), .ra(_u_VRAM_ra), .d(_u_VRAM_d), .clk(_u_VRAM_clk));\r
+vram u_VRAM (.p_reset(p_reset), .m_clock(m_clock), .q(_u_VRAM_q), .wren(_u_VRAM_wren), .wraddress(_u_VRAM_wraddress), .rdaddress(_u_VRAM_rdaddress), .data(_u_VRAM_data), .clock(_u_VRAM_clock));\r
 \r
-   assign  _u_VRAM_d = i_Wdata;\r
-   assign  _u_VRAM_ra = ((_net_3)?i_Radrs:14'b0)|\r
+   assign  _u_VRAM_clock = m_clock;\r
+   assign  _u_VRAM_data = i_Wdata;\r
+   assign  _u_VRAM_rdaddress = ((_net_3)?i_Radrs:14'b0)|\r
     ((_reg_1)?r_Radrs_hld:14'b0);\r
-   assign  _u_VRAM_wa = i_Wadrs;\r
-   assign  _u_VRAM_we = fi_Wr_req|\r
+   assign  _u_VRAM_wraddress = i_Wadrs;\r
+   assign  _u_VRAM_wren = fi_Wr_req|\r
     ((_net_0)?1'b0:1'b0);\r
    assign  _net_0 = ~fi_Wr_req;\r
    assign  _net_3 = fi_Rd_req|_reg_2;\r
    assign  _net_4 = fi_Rd_req|_reg_1|_reg_2;\r
    assign  o_Rdata = _u_VRAM_q;\r
    assign  fo_Rd_ack = _reg_1;\r
-always @(posedge p_reset)\r
+always @(negedge p_reset)\r
  begin\r
-if (p_reset)\r
+if (~p_reset)\r
      r_Radrs_hld <= 14'b00000000000000;\r
 end\r
-always @(posedge m_clock or posedge p_reset)\r
+always @(posedge m_clock or negedge p_reset)\r
   begin\r
-if (p_reset)\r
+if (~p_reset)\r
      _reg_1 <= 1'b0;\r
 else if ((_net_4)) \r
       _reg_1 <= _reg_2|fi_Rd_req;\r
 end\r
-always @(posedge m_clock or posedge p_reset)\r
+always @(posedge m_clock or negedge p_reset)\r
   begin\r
-if (p_reset)\r
+if (~p_reset)\r
      _reg_2 <= 1'b0;\r
 else if ((_reg_2)) \r
       _reg_2 <= 1'b0;\r
 end\r
 endmodule\r
 /*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Wed Jul 20 21:25:25 2011\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Fri Aug 12 17:25:23 2011\r
  Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
 */\r