VGA System Complete

[oca1/test.git] / VGADisplay / Verilog / vram_ctrl.v

diff --git a/VGADisplay/Verilog/vram_ctrl.v b/VGADisplay/Verilog/vram_ctrl.v
index b901273..528ffa5 100644 (file)
--- a/VGADisplay/Verilog/vram_ctrl.v
+++ b/VGADisplay/Verilog/vram_ctrl.v
@@ -1,6 +1,6 @@
 /*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Nov 19 16:50:41 2011\r
- Licensed to :LIMITED EVALUATION USER:\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Sun Dec 25 22:47:10 2011\r
+ Licensed to Yujiro_Kaneko::zyangalianhamster01@gmail.com :NON PROFIT USER:\r
 */\r
 \r
 module vram_ctrl ( p_reset , m_clock , i_Wdata , i_Wadrs , i_Radrs , o_Rdata , fi_Wr_req , fi_Rd_req , fo_Rd_ack );\r
@@ -61,6 +61,6 @@ else if ((_reg_2))
 end\r
 endmodule\r
 /*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Nov 19 16:50:42 2011\r
- Licensed to :LIMITED EVALUATION USER:\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Sun Dec 25 22:47:11 2011\r
+ Licensed to Yujiro_Kaneko::zyangalianhamster01@gmail.com \r
 */\r