VRAM FIFO VGAgen VGAtop連結完了

[oca1/test.git] / VGADisplay / src / vga_gen.nsl

diff --git a/VGADisplay/src/vga_gen.nsl b/VGADisplay/src/vga_gen.nsl
index 29055fb..d6b3ce5 100644 (file)
--- a/VGADisplay/src/vga_gen.nsl
+++ b/VGADisplay/src/vga_gen.nsl
@@ -31,11 +31,11 @@ declare vga_gen interface {
 
        input  i_wrdata1[8] ;
        input  i_wrdata2[8] ;
-       
-       func_in fi_fifo1_write( i_wrdata1 ) ;
-       func_in fi_fifo2_write( i_wrdata2 ) ;
-       func_in fi_fifo1_reset() ;
-       func_in fi_fifo2_reset() ;
+       input  i_wradrs1[8] ;
+       input  i_wradrs2[8] ;
+
+       func_in fi_fifo1_write( i_wradrs1, i_wrdata1 ) ;
+       func_in fi_fifo2_write( i_wradrs2, i_wrdata2 ) ;
 
        output outled ;
        output o_vcnt[10] ;
@@ -47,6 +47,9 @@ module vga_gen {
        func_self fs_fifo1_exec() ;
        func_self fs_fifo2_exec() ;
 
+       func_self fs_fifo1_reset() ;
+       func_self fs_fifo2_reset() ;
+
        reg r_bit_number[5] = 0 ;
 
        reg r_vsync = 0 ;
@@ -57,10 +60,14 @@ module vga_gen {
        reg testled = 0 ;
        reg r_outcnt[3] = 0 ;
        reg r_outclr[7] = 0 ;
+       reg r_vcnt_hld = 0 ;
        
        wire w_rddata1[24] ;
        wire w_rddata2[24] ;
 
+       reg r_rdadrs1[8] = 0 ;
+       reg r_rdadrs2[8] = 0 ;
+
        vga_ram u_FIFO ;
        
        {
@@ -70,21 +77,34 @@ module vga_gen {
 
                u_FIFO.i_we1            = fi_fifo1_write ;
                u_FIFO.i_we2            = fi_fifo2_write ;
-               u_FIFO.i_wdata1         = i_wrdata1 ;
-               u_FIFO.i_wdata2         = i_wrdata2 ;
-               u_FIFO.i_fifo1_rst      = fi_fifo1_reset ;
-               u_FIFO.i_fifo2_rst      = fi_fifo2_reset ;
+               u_FIFO.i_wrdata1        = i_wrdata1 ;
+               u_FIFO.i_wrdata2        = i_wrdata2 ;
+               u_FIFO.i_wradrs1        = i_wradrs1 ;
+               u_FIFO.i_wradrs2        = i_wradrs2 ;
                u_FIFO.i_re1            = fs_fifo1_read ;               
                u_FIFO.i_re2            = fs_fifo2_read ;
                w_rddata1                       = u_FIFO.o_rddata1 ;
                w_rddata2                       = u_FIFO.o_rddata2 ;
+               u_FIFO.i_rdadrs1        = r_rdadrs1 ;
+               u_FIFO.i_rdadrs2        = r_rdadrs2 ;
                o_vcnt                          = r_vcnt ;
 
+               r_vcnt_hld                      := r_vcnt[0] ;
+
                /* LED test */
                outled = testled ;
                o_vsync = r_vsync ;
                o_hsync = r_hsync ;
 
+               any {
+                       ~r_vcnt_hld &  r_vcnt[0] : {
+                               fs_fifo1_reset() ;
+                       }
+                        r_vcnt_hld & ~r_vcnt[0] : {
+                               fs_fifo2_reset() ;
+                       }
+               }
+
                /* test led count routine */
                any {
                        cnt == VCNT_1SEC : {
@@ -108,6 +128,7 @@ module vga_gen {
                        }
                }
                
+               // HACTMAX640 VACTMAX480
                if( ( r_hcnt < H_ACT_MAX ) && ( r_vcnt < V_ACT_MAX ) ) {
 
                        any {
@@ -203,4 +224,20 @@ module vga_gen {
                        
                }
        }
+       
+       func fs_fifo1_read {
+               r_rdadrs1 := r_rdadrs1 + 8'd3 ;
+       }
+
+       func fs_fifo2_read {
+               r_rdadrs2 := r_rdadrs2 + 8'd3 ;         
+       }
+       
+       func fs_fifo1_reset {
+               r_rdadrs1 := 8'd0 ;
+       }
+       
+       func fs_fifo2_reset {
+               r_rdadrs2 := 8'd0 ;
+       }
 } //module end
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