#include "vga_gen.nsl"\r
#include "exp_ctrl.nsh"\r
//#include "from_ctrl.nsh"\r
+#include "push_sw.nsl"\r
\r
#define CNT1S 26'd50000000\r
\r
#define CNT10mS 26'd500000 // 10 [ms]\r
#define CNT2mS 26'd100000 // 2 [ms]\r
\r
-/*\r
-#define CNT1S 26'd500 // 1 [s]\r
-#define CNTHS 26'd250 // 0.5 [s]\r
-#define CNTQS 26'd125 // 0.25 [s]\r
-#define CNTHQS 26'd62 // 0.125 [s]\r
-#define CNT10mS 26'd50 // 10 [ms]\r
-#define CNT2mS 26'd10 // 2 [ms]\r
-*/\r
-\r
declare vga_top {\r
- input i_sw ;\r
+ input i_sw[4] ;\r
\r
output o_vsync ;\r
output o_hsync ;\r
reg r_vram_rddata[16] = 0 ;\r
reg r_vram_start_adrs[14] = 0 ;\r
reg r_hld_vram_start = 0 ;\r
+ reg r_fifo_rst = 0 ;\r
\r
wire w_wrdata1[8] ;\r
wire w_wrdata2[8] ;\r
\r
reg r_wradrs1[8] = 0 ;\r
reg r_wradrs2[8] = 0 ;\r
+ \r
+ reg r_out_sel = 0 ;\r
\r
func_self test_write() ;\r
\r
proc_name p_wait( r_wait_val ) ;\r
\r
vga_gen u_VGA ;\r
- exp_ctrl u_EXP ;\r
+ push_sw u_BTN[4] ;\r
+// exp_ctrl u_EXP ;\r
// from_ctrl u_FROMC ;\r
\r
{\r
+ /* IF */\r
+ u_BTN[0].i_sw = i_sw[0] ;\r
+ u_BTN[1].i_sw = i_sw[1] ;\r
+ u_BTN[2].i_sw = i_sw[2] ;\r
+ u_BTN[3].i_sw = i_sw[3] ;\r
+ \r
+ if(u_BTN[0].fo_sw_enb) r_out_sel := ~r_out_sel ; \r
+ \r
+ any {\r
+ r_out_sel == 0b0 : {\r
+ o_vga_r = 4#(u_VGA.o_dummy_rgb[2]) ;\r
+ o_vga_g = 4#(u_VGA.o_dummy_rgb[1]) ;\r
+ o_vga_b = 4#(u_VGA.o_dummy_rgb[0]) ;\r
+ }\r
+ else : {\r
+ o_vga_r = u_VGA.o_vga_r ;\r
+ o_vga_g = u_VGA.o_vga_g ;\r
+ o_vga_b = u_VGA.o_vga_b ;\r
+ }\r
+ }\r
+\r
/* VGA */\r
o_vsync = u_VGA.o_vsync ;\r
o_hsync = u_VGA.o_hsync ;\r
- o_vga_r = u_VGA.o_vga_r ;\r
- o_vga_g = u_VGA.o_vga_g ;\r
- o_vga_b = u_VGA.o_vga_b ;\r
- u_VGA.i_clk50M = m_clock ;\r
+ u_VGA.i_clk50 = m_clock ;\r
r_hld_vram_start := u_VGA.o_vcnt[0] ;\r
+ u_VGA.i_fifo_rst = r_fifo_rst ;\r
+\r
+ \r
\r
trigger := { trigger[1:0], 0b1 } ;\r
if(trigger == 3'b011) fs_init() ;\r
\r
+/*\r
if(~r_reset) {\r
any {\r
r_hld_vram_start & ~u_VGA.o_vcnt[0] : { //FIFO1\82ð\93Ç\82Ý\8fo\82·\83^\83C\83~\83\93\83O\r
if(u_VGA.o_vcnt < 10'd480) fs_fifo1_charge() ;\r
}\r
}\r
- \r
}\r
+*/\r
\r
any {\r
r_sec_cnt == CNT1S : {\r
\r
\r
r_cnt := ~r_cnt ;\r
- o_LED = { 0b00000, i_sw, r_LED, u_VGA.outled } ;\r
+ o_LED = { 0b00, i_sw, r_LED, u_VGA.o_led } ;\r
\r
u_VGA.m_clock = r_cnt ;\r
u_VGA.p_reset = r_reset ;\r
\r
func fs_init seq {\r
/* VRAM\8f\89\8aú\89»\83\8b\81[\83`\83\93 */\r
- for(r_init_cnt:=0;r_init_cnt<9600;r_init_cnt++) {\r
- u_EXP.fi_Wr_req(r_init_cnt, r_init_cnt[7:0]) ;\r
- }\r
+// for(r_init_cnt:=0;r_init_cnt<9600;r_init_cnt++) {\r
+// u_EXP.fi_Wr_req(r_init_cnt, r_init_cnt[7:0]) ;\r
+// }\r
\r
- for(r_init_cnt:=0;r_init_cnt<40;r_init_cnt++) {\r
- u_EXP.fi_Rd_req(r_vram_adrs1) ;\r
- r_vram_rddata := u_EXP.o_Rdata ;\r
- {\r
- fs_fifo1_write(r_wradrs1, r_vram_rddata[15:8]) ;\r
- r_wradrs1++ ;\r
- }\r
- {\r
- fs_fifo1_write(r_wradrs1, r_vram_rddata[7:0]) ;\r
- r_wradrs1++ ;\r
- }\r
- \r
- r_vram_adrs1++ ;\r
- }\r
+// for(r_init_cnt:=0;r_init_cnt<40;r_init_cnt++) {\r
+// u_EXP.fi_Rd_req(r_vram_adrs1) ;\r
+// r_vram_rddata := u_EXP.o_Rdata ;\r
+// {\r
+// fs_fifo1_write(r_wradrs1, r_vram_rddata[15:8]) ;\r
+// r_wradrs1++ ;\r
+// }\r
+// {\r
+// fs_fifo1_write(r_wradrs1, r_vram_rddata[7:0]) ;\r
+// r_wradrs1++ ;\r
+// }\r
+// \r
+// r_vram_adrs1++ ;\r
+// }\r
\r
- r_wradrs1 := 0 ; //act!!\r
+// r_wradrs1 := 0 ; //act!!\r
\r
\r
- for(r_init_cnt:=0;r_init_cnt<40;r_init_cnt++) {\r
- u_EXP.fi_Rd_req(r_vram_adrs2) ;\r
- r_vram_rddata := u_EXP.o_Rdata ;\r
- {\r
- fs_fifo2_write(r_wradrs2, r_vram_rddata[15:8]) ;\r
- r_wradrs2++ ;\r
- }\r
- {\r
- fs_fifo2_write(r_wradrs2, r_vram_rddata[7:0]) ;\r
- r_wradrs2++ ;\r
- }\r
-\r
- r_vram_adrs2++ ;\r
- }\r
+// for(r_init_cnt:=0;r_init_cnt<40;r_init_cnt++) {\r
+// u_EXP.fi_Rd_req(r_vram_adrs2) ;\r
+// r_vram_rddata := u_EXP.o_Rdata ;\r
+// {\r
+// fs_fifo2_write(r_wradrs2, r_vram_rddata[15:8]) ;\r
+// r_wradrs2++ ;\r
+// }\r
+// {\r
+// fs_fifo2_write(r_wradrs2, r_vram_rddata[7:0]) ;\r
+// r_wradrs2++ ;\r
+// }\r
+//\r
+// r_vram_adrs2++ ;\r
+// }\r
\r
- r_wradrs2 := 0 ; //ACT!!\r
+// r_wradrs2 := 0 ; //ACT!!\r
+\r
+// r_vram_start_adrs := r_vram_start_adrs + 14'd40 ;\r
+\r
+ r_fifo_rst := 1 ;\r
+ ;;;\r
+ r_fifo_rst := 0 ;\r
+ ;;;\r
\r
- r_vram_start_adrs := r_vram_start_adrs + 14'd40 ;\r
- r_reset := 0 ;\r
-// test_write() ;\r
+ for(r_init_cnt:=0; r_init_cnt<512; r_init_cnt++ ) {\r
+ u_VGA.fi_fifo_write(r_init_cnt[7:0]) ;\r
+ u_VGA.fi_fifo_write(r_init_cnt[7:0]) ;\r
+ } \r
+\r
+ r_reset := 0 ; \r
}\r
- \r
+\r
+/* \r
func fs_fifo1_write {\r
u_VGA.fi_fifo1_write(w_wradrs1, w_wrdata1) ;\r
}\r
func fs_fifo2_write {\r
u_VGA.fi_fifo2_write(w_wradrs2, w_wrdata2) ; \r
}\r
+*/\r
\r
+/*\r
func fs_fifo1_charge seq {\r
for(r_init_cnt:=0;r_init_cnt<40;r_init_cnt++) {\r
u_EXP.fi_Rd_req(r_vram_adrs1) ;\r
r_wradrs1:= 0 ;\r
if( r_vram_adrs1 == 14'd9600 ) r_vram_adrs1 := 0 ;\r
}\r
+*/\r
\r
+/*\r
func fs_fifo2_charge seq {\r
\r
for(r_init_cnt:=0;r_init_cnt<40;r_init_cnt++) {\r
}\r
}\r
}\r
+*/\r
\r
proc p_wait {\r
any {\r
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